Inventor
Raghavan KUMAR
Inventor
US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing27%
G06NComputing arrangements based on specific computational models20%
H04LTransmission of digital information, e.g. telegraphic communication18%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy12%
H10BElectronic memory devices5%
G11CStatic stores4%
H01LSemiconductor devices4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
H10DInorganic electric semiconductor devices2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,368,574Side-channel resistant multiplicatively masked encryption engine with zero-value attack detection202512,361,269LSTM circuit with selective input computation202512,316,735Technologies for memory and I/O efficient operations on homomorphically encrypted data202512,137,169Low latency post-quantum signature verification for fast secure-boot202412,047,485Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations202411,917,053Combined SHA2 and SHA3 based XMSS hardware accelerator202411,790,217LSTM circuit with selective input computation202311,783,160Memoryless weight storage hardware for neural networks202311,770,262Odd index precomputation for authentication path computation202311,768,966Secure PUF-based device authentication using adversarial challenge selection202311,770,258Accelerators for post-quantum cryptography secure hash-based signing and verification202311,751,404FinFET transistor based resistive random access memory202311,750,402Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification202311,726,950Compute near memory convolution accelerator202311,727,260Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits202311,663,452Processor array for processing sparse binary neural networks202311,625,584Reconfigurable memory compression techniques for deep neural networks202311,522,012Deep in memory architecture using resistive switches202211,502,696In-memory analog neural cache202211,456,877Unified accelerator for classical and post-quantum digital signature schemes in computing environments202211,455,431Secure PUF-based device authentication using adversarial challenge selection202211,416,165Low synch dedicated accelerator with in-memory computation capability202211,405,213Low latency post-quantum signature verification for fast secure-boot202211,347,994Weight prefetch for in-memory neural network execution202211,347,477Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations202211,303,429Combined SHA2 and SHA3 based XMSS hardware accelerator202211,281,963Programmable neuron core with on-chip learning and stochastic time step control202211,240,039Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification202211,223,483Odd index precomputation for authentication path computation202211,218,320Accelerators for post-quantum cryptography secure hash-based signing and verification202211,205,017Post quantum public key signature operation for reconfigurable circuit devices202111,195,079Reconfigurable neuro-synaptic cores for spiking neural network202111,157,799Neuromorphic circuits for storing and generating connectivity information202111,151,046Programmable interface to in-memory cache processor202111,138,499Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to INTEL CORP (35)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 35 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 35 | 2021–2025 |