LexDanaLexDanabeta
Inventor

David R. Stiles

Inventor
Los Gatos, CA, US

Overview

44→
Patents
1992–2017
Patent span
Physics
Primary field (CPC G)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing42%
H04JMultiplex communication18%
H04LTransmission of digital information, e.g. telegraphic communication15%
G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
A61BDiagnosis3%
H04BTransmission3%
H04QSelecting3%
A61MDevices for introducing media into, or onto, the body1%
E02DFoundations1%
PatentTitleYear
9,644,337'Systems and methods for positioning and anchoring columns'20179,393,361'Method to determine a material distribution'20169,020,224'Volume of efficacy model capture'20159,008,752'Method to determine distribution of a material by an infused magnetic resonance image contrast agent'20158,335,552'Method and apparatus for instrument placement'20128,228,958'Ring network element and the ring network architectures it enables'20127,460,554'Any size and location of concatenated packet data across SONET frames in a SONET signal'20087,324,539'Method and apparatus for processing channelized and unchannelized data within a signal'20087,277,447'Onboard RAM based FIFO with pointers to buffer overhead bytes of synchronous payload envelopes in synchronous optical networks'20077,272,157'Any size and location of concatenated packet data across SONET frames in a SONET signal'20077,209,436'Method and apparatus for variable rate pipes'20077,158,540'Ring network element and the ring network architectures it enables'20077,050,395'Method and apparatus for disabling an interface between network element data processing units'20067,016,300'Protection mechanism for an optical ring'20066,993,047'Any size and location of concatenated packet data across SONET frames in a SONET signal'20066,990,121'Method and apparatus for switching data of different protocols'20066,975,589'Method and apparatus for a hybrid variable rate pipe'20056,959,008'Alignment of TDM-based signals for packet transmission using framed and unframed operations'20056,765,916'Method and apparatus for processing of multiple protocols within data transmission signals'20046,499,123'Method and apparatus for debugging an integrated circuit'20026,425,075'Branch prediction device with two levels of branch prediction cache'20026,212,629'Method and apparatus for executing string instructions'20016,067,616'Branch prediction device with two levels of branch prediction cache'20006,021,471'Multiple level cache control system with address and data pipelines'20005,905,997'Set-associative cache memory utilizing a single bank of physical memory'19995,881,265'Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts'19995,832,259'Apparatus for superscalar instruction pre-decoding using cached instruction lengths'19985,826,052'Method and apparatus for concurrent access to multiple physical caches'19985,781,753'Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions'19985,768,575'Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions'19985,764,556'Method and apparatus for performing floating point addition'19985,748,932'Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence'19985,682,492'Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts'19975,649,137'Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency'19975,515,518'Two-level branch prediction cache'19965,513,330'Apparatus for superscalar instruction predecoding using cached instruction lengths'19965,511,175'Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency'19965,442,757'Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts'19955,327,547'Two-level branch prediction cache'19945,230,068'Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence'19935,226,130'Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency'19935,226,126'Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags'19935,163,140'Two-level branch prediction cache'19925,093,778'Integrated single structure branch prediction cache'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–1994Patents assigned to NEXGEN MICROSYSTEMS (6)· patent assignee history
1992–2002Based in Sunnyvale, CA, US· patent location history
1995–1996Patents assigned to NEXGEN INC (4)· patent assignee history
1997–2002Patents assigned to ADVANCED MICRO DEVICES INC (14)· patent assignee history
1998–2012Based in Los Gatos, CA, US· patent location history
2004–2008Patents assigned to REDBACK NETWORKS INC (13)· patent assignee history
2012–2016Patents assigned to MEDTRONIC INC (4)· patent assignee history
2012Based in Maple Grove, MN, US· patent location history
2015–2016Based in Danvers, MA, US· patent location history
2017Based in Pompano Beach, FL, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC141997–2002
REDBACK NETWORKS INC132004–2008
NEXGEN MICROSYSTEMS61992–1994
MEDTRONIC INC42012–2016
NEXGEN INC41995–1996
Locations
LocationPatentsSpan
Los Gatos, California, US221998–2012
Sunnyvale, California, US171992–2002
Danvers, Massachusetts, US32015–2016
Pompano Beach, Florida, US12017
Maple Grove, Minnesota, US12012