Inventor
Max M. Yeung
Inventor
San Jose, CA, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1071%
H03MCoding14%
H10DInorganic electric semiconductor devices14%
PatentTitleYear
7,117,420'Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories'20066,815,812'Direct alignment of contacts'20046,784,102'Laterally interconnecting structures'20046,768,142'Circuit component placement'20046,683,476'Contact ring architecture'20046,657,870'Die power distribution system'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2006Patents assigned to LSI LOGIC CORP (6)· patent assignee history
2003–2006Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 6 | 2003–2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 6 | 2003–2006 |