Inventor
Christopher Dennis Bencher
Inventor
Cupertino, CA, US
Overview
Patents· 92 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
C23CCoating metallic material10%
H01LSemiconductor devices6%
G02BOptical elements, systems or apparatus4%
H10DInorganic electric semiconductor devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%
B08BCleaning in general2%
PatentTitleYear
10,983,444Systems and methods of using solid state emitter arrays202110,935,890Half tone scheme for maskless lithography202110,921,714Reserving spatial light modulator sections to address field non-uniformities202110,908,507Micro LED array illumination source202110,877,199Method for manufacturing a polarizer apparatus, polarizer apparatus, and display system having a polarizer apparatus202010,761,430Method to enhance the resolution of maskless lithography while maintaining a high image contrast202010,705,433Reserving spatial light modulator sections to address field non-uniformities202010,705,431Quarter wave light splitting202010,684,555Spatial light modulator with variable intensity diodes202010,599,044Digital lithography with extended field size202010,591,815Shifting of patterns to reduce line waviness202010,571,809Half tone scheme for maskless lithography202010,559,730Collimated LED light field display202010,509,328Fabrication and use of dose maps and feature size maps during substrate processing201910,503,076Reserving spatial light modulator sections to address field non-uniformities201910,495,979Half tone scheme for maskless lithography201910,495,975Line edge roughness reduction via step size alteration201910,490,599Collimated, directional micro-LED light field display201910,488,762Method to reduce data stream for spatial light modulator201910,474,041Digital lithography with extended depth of focus201910,416,550Method to reduce line waviness201910,394,130Quarter wave light splitting201910,289,003Line edge roughness reduction via step size alteration201910,256,382Collimated OLED light field display201910,108,093Controlling photo acid diffusion in lithography processes201810,073,350Maskless lithography for web based processing201810,012,910Pattern generators employing processors to vary delivery dose of writing beams according to photoresist thickness, and associated methods201810,014,184Methods and apparatus for forming a resist array using chemical mechanical planarization201810,014,174Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning20189,927,696'Method to reduce line waviness'20189,915,621'Extreme ultraviolet (EUV) substrate inspection system with simplified optics and method of manufacturing thereof'20189,823,573'Correction of non-uniform patterns using time-shifted exposures'20179,798,240'Controlling photo acid diffusion in lithography processes'20179,791,786'Method to reduce line waviness'20179,748,148'Localized stress modulation for overlay and EPE'20179,659,771'Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning'20179,646,642'Resist fortification for magnetic media patterning'20179,484,274'Methods for reducing semiconductor substrate strain variation'20169,478,421'Optically tuned hardmask for multi-patterning applications'20169,411,237'Resist hardening and development processes for semiconductor device manufacturing'20169,395,631'Multi-beam pattern generators employing yaw correction when writing upon large substrates, and associated methods'20169,383,649'Digital grey tone lithography for 3D pattern formation'20169,377,692'Electric/magnetic field guided acid diffusion'20169,337,051'Method for critical dimension reduction using conformal carbon films'20169,337,314'Technique for selectively processing three dimensional device'20169,177,796'Optically tuned hardmask for multi-patterning applications'20158,658,242'Resist fortification for magnetic media patterning'20148,357,618'Frequency doubling using a photo-resist template mask'20138,338,316'Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants'20128,293,460'Double exposure patterning with carbonaceous hardmask'20128,183,150'Semiconductor device having silicon carbide and conductive pathway interface'20128,148,269'Boron nitride and boron-nitride derived materials deposition method'20128,084,310'Self-aligned multi-patterning for advanced critical dimension contacts'20117,989,366'Dopant activation in doped semiconductor substrates'20117,968,473'Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants'20117,910,476'Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop'20117,901,869'Double patterning with a double layer cap on carbonaceous hardmask'20117,846,849'Frequency tripling using spacer mask having interposed regions'20107,811,924'Air gap formation and integration using a patterning cap'20107,807,578'Frequency doubling using spacer mask'20107,737,040'Method of reducing critical dimension bias during fabrication of a semiconductor device'20107,718,081'Techniques for the use of amorphous carbon (APF) for various etch and litho integration schemes'20107,709,396'Integral patterning of large features along with array using spacer mask patterning process flow'20107,608,300'Methods and devices to reduce defects in dielectric stack structures'20097,598,183'Bi-layer capping of low-K dielectric films'20097,588,990'Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer'20097,547,621'LPCVD gate hard mask'20097,507,677'Removable amorphous carbon CMP stop'20097,365,014'Reticle fabrication using a removable hard mask'20087,335,462'Method of depositing an amorphous carbon layer'20087,332,262'Photolithography scheme using a silicon containing resist'20087,223,526'Method of depositing an amorphous carbon layer'20077,148,156'Removable amorphous carbon CMP stop'20067,105,460'Nitrogen-free dielectric anti-reflective coating and hardmask'20067,105,442'Ashable layers for reducing critical dimensions of integrated circuit features'20066,967,072'Photolithography scheme using a silicon containing resist'20056,951,826'Silicon carbide deposition for use as a low dielectric constant anti-reflective coating'20056,946,401'Plasma treatment for copper oxide reduction'20056,927,178'Nitrogen-free dielectric anti-reflective coating and hardmask'20056,924,191'Method for fabricating a gate structure of a field effect transistor'20056,913,868'Conductive bi-layer e-beam resist with amorphous carbon'20056,852,647'Removable amorphous carbon CMP stop'20056,853,043'Nitrogen-free antireflective coating for use with photolithographic patterning'20056,841,341'Method of depositing an amorphous carbon layer'20056,797,646'Method of nitrogen doping of fluorinated silicate glass (FSG) while removing the photoresist layer'20046,780,753'Airgap for semiconductor devices'20046,700,202'Semiconductor device having reduced oxidation interface'20046,635,583'Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating'20036,573,030'Method for depositing an amorphous carbon layer'20036,541,397'Removable amorphous carbon CMP stop'20036,365,518'Method of processing a substrate in a processing chamber'20026,355,571'Method and apparatus for reducing copper oxidation and contamination in a semiconductor device'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to APPLIED MATERIALS INC (91)· patent assignee history
2002–2014Based in San Jose, CA, US· patent location history
2002–2012Based in Sunnyvale, CA, US· patent location history
2011–2013Patents assigned to BENCHER CHRISTOPHER DENNIS (4)· patent assignee history
2011–2013Patents assigned to MIAO LI YAN (3)· patent assignee history
2012–2014Patents assigned to BENCHER CHRISTOPHER D (3)· patent assignee history
2012Patents assigned to CHEN YONGMEI (2)· patent assignee history
2015–2021Based in Cupertino, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 91 | 2002–2021 |
| BENCHER CHRISTOPHER DENNISself | 4 | 2011–2013 |
| BENCHER CHRISTOPHER Dself | 3 | 2012–2014 |
| MIAO LI YAN | 3 | 2011–2013 |
| CHEN YONGMEI | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 46 | 2015–2021 |
| San Jose, California, US | 34 | 2002–2014 |
| Sunnyvale, California, US | 12 | 2002–2012 |