LexDanaLexDanabeta
Inventor

Sanjay Mehrotra

Inventor
Milpitas, CA, US

Overview

76→
Patents
1986–2021
Patent span
Physics
Primary field (CPC G)

Patents· 76 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores49%
G06FElectric digital data processing37%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
A61JContainers specially adapted for medical or pharmaceutical purposes2%
G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data2%
H04NPictorial communication, e.g. television2%
H10BElectronic memory devices2%
A61BDiagnosis1%
PatentTitleYear
11,109,768Tonometry based blood pressure measurements using a two-dimensional force sensor array202111,089,269System and method for tracking content in a medicine container202110,687,032System and method for tracking content in a medicine container202010,091,468System and method for tracking content in a medicine container20188,125,834'Device and method for controlling solid-state memory system'20127,890,694'Latched address multi-chunk write to EEPROM'20117,839,685'Soft errors handling in EEPROM devices'20107,688,643'Device and method for controlling solid-state memory system'20107,616,484'Soft errors handling in EEPROM devices'20097,548,461'Soft errors handling in EEPROM devices'20097,492,660'Flash EEprom system'20097,460,399'Flash EEprom system'20087,447,069'Flash EEprom system'20087,437,631'Soft errors handling in EEPROM devices'20087,397,713'Flash EEprom system'20087,362,618'Flash EEprom system'20087,283,397'Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks'20077,266,017'Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system'20077,190,617'Flash EEprom system'20076,914,846'Flash EEprom system'20056,829,673'Latched address multi-chunk write to EEPROM'20046,763,480'Flash EEprom system'20046,757,842'Flash EEprom system'20046,715,044'Device and method for controlling solid-state memory system'20046,684,345'Flash EEprom system'20046,542,956'Latched address multi-chunk write to EEPROM'20036,523,132'Flash EEprom system'20036,519,185'Flash EEprom system'20036,462,992'Flash EEprom system'20026,414,876'Flash EEprom system'20026,373,747'Flash EEprom system'20026,317,812'Device and method for controlling solid-state memory system'20016,304,485'Flash EEprom system'20016,282,130'EEPROM memory chip with multiple use pinouts'20016,157,983'Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM'20006,149,316'Flash EEprom system'20006,148,363'Device and method for controlling solid-state memory system'20006,069,039'Plane decode/virtual sector architecture'20006,049,899'Soft errors handling in EEPROM devices'20005,999,446'Multi-state flash EEprom system with selective multi-sector erase'19995,991,517'Flash EEprom system with cell by cell programming verification'19995,936,971'Multi-state flash EEprom system with cache memory'19995,890,192'Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM'19995,877,986'Multi-state Flash EEprom system on a card that includes defective cell substitution'19995,862,080'Multi-state flash EEprom system with defect handling'19995,806,070'Device and method for controlling solid-state memory system'19985,798,968'Plane decode/virtual sector architecture'19985,719,808'Flash EEPROM system'19985,693,570'Process for manufacturing a programmable power generation circuit for flash EEPROM memory systems'19975,671,229'Flash eeprom system with defect handling'19975,659,550'Latent defect handling in EEPROM devices'19975,657,332'Soft errors handling in EEPROM devices'19975,621,685'Programmable power generation circuit for flash EEPROM memory systems'19975,602,987'Flash EEprom system'19975,596,532'Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range'19975,592,420'Programmable power generation circuit for flash EEPROM memory systems'19975,568,424'Programmable power generation circuit for flash EEPROM memory systems'19965,563,825'Programmable power generation circuit for flash eeprom memory systems'19965,535,328'Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells'19965,532,962'Soft errors handling in EEPROM devices'19965,532,964'Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells'19965,508,971'Programmable power generation circuit for flash EEPROM memory systems'19965,504,760'Mixed data encoding EEPROM system'19965,495,442'Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells'19965,430,859'Solid state memory system including plural memory chips and a serialized bus'19955,428,621'Latent defect handling in EEPROM devices'19955,422,842'Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells'19955,418,752'Flash EEPROM system with erase sector select'19955,396,468'Streamlined write operation for EEPROM system'19955,369,615'Method for optimum erasing of EEPROM'19945,315,541'Segmented column memory array'19945,297,148'Flash eeprom system'19945,270,979'Method for optimum erasing of EEPROM'19935,172,338'Multi-state EEprom read and write circuits and techniques'19925,163,021'Multi-state EEprom read and write circuits and techniques'19924,612,640'Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986Based in San Jose, CA, US· patent location history
1992–1995Patents assigned to SUNDISK CORP (10)· patent assignee history
1992–2012Based in Milpitas, CA, US· patent location history
1995–2010Patents assigned to WESTERN DIGITAL CORP (4)· patent assignee history
1996–2011Patents assigned to SANDISK CORP (57)· patent assignee history
2001Based in Los Altos, CA, US· patent location history
2004Based in Milipitas, CA, US· patent location history
2012Patents assigned to GUPTA ANIL (1)· patent assignee history
2018–2021Patents assigned to UNIV NORTHWESTERN (4)· patent assignee history
2018–2021Based in Winnetka, IL, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK CORP571996–2011
SUNDISK CORP101992–1995
UNIV NORTHWESTERN42018–2021
WESTERN DIGITAL CORP41995–2010
GUPTA ANIL12012
Locations
LocationPatentsSpan
Milpitas, California, US691992–2012
Winnetka, Illinois, US42018–2021
Milipitas, California, US12004
Los Altos, California, US12001
San Jose, California, US11986