Inventor
Heng-Hsin Liu
Inventor
New Taipei, TW
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H01LSemiconductor devices14%
G06FElectric digital data processing7%
G01BMeasuring length, thickness or similar linear dimensions7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
G03BApparatus or arrangements for taking photographs or for projecting or viewing them3%
H05BElectric heating3%
G06TImage data processing or generation, in general2%
PatentTitleYear
10,895,461Multi-day, multi-person, and multi-modal trip planning system202110,831,751Query parallelism method202010,831,110Lithographic overlay correction and lithographic process202010,747,128Exposure method and exposure apparatus202010,572,480Adaptive intersect query processing202010,528,562Adaptive intersect query processing202010,514,247Wafer alignment mark scheme201910,061,215Patterning method and patterning apparatus for fabricating a resist pattern20189,978,625Semiconductor method and associated apparatus20189,928,884'Elastic memory expansion chip architecture'20189,892,161'Adaptive intersect query processing'20189,863,754'Wafer alignment mark scheme'20189,841,687'Synchronized integrated metrology for overlay-shift reduction'20179,814,097'Baking apparatus for priming substrate'20179,781,773'Method of heating/cooling a substrate'20179,772,561'Semiconductor manufacturing method and tool'20179,766,559'Edge-dominant alignment method in exposure scanner system'20179,709,904'Lithography apparatus having dual reticle edge masking assemblies and method of use'20179,658,536'In-line inspection and clean for immersion lithography'20179,640,487'Wafer alignment mark scheme'20179,601,324'Method of making wafer assembly'20179,587,929'Focus metrology method and photolithography method and system'20179,576,004'Free space management in databases'20179,563,946'Overlay metrology method and overlay control method and system'20179,466,101'Detection of defects on wafer during semiconductor fabrication'20169,282,592'Rotatable heating-cooling plate and element in proximity thereto'20169,228,827'Flexible wafer leveling design for various orientation of line/trench'20169,196,515'Litho cluster and modulization to enhance productivity'20159,188,876'Method of determining overlay error and control system for dynamic control of reticle position'20159,176,958'Method and apparatus for music searching'20159,164,398'Overlay metrology method'20159,123,583'Overlay abnormality gating by Z data'20159,111,982'Wafer assembly with carrier wafer'20159,081,297'Lithography apparatus having dual reticle edge masking assemblies and method of use'20158,924,402'Generating a test workload for a database'20148,906,599'Enhanced scanner throughput system and method'20148,903,532'Litho cluster and modulization to enhance productivity'20148,860,941'Tool induced shift reduction determination for overlay metrology'20148,703,368'Lithography process'20148,674,355'Integrated circuit test units with integrated physical and electrical test regions'20148,592,287'Overlay alignment mark and method of detecting overlay alignment error using the mark'20138,199,314'System and method for improving immersion scanner overlay performance'20128,183,701'Structure of stacking scatterometry based overlay marks for marks footprint reduction'20128,101,530'Lithography patterning method'20128,068,208'System and method for improving immersion scanner overlay performance'20117,901,854'Wafer edge exposure unit'20117,796,249'Mask haze early detection'20107,571,021'Method and system for improving critical dimension uniformity'20097,333,173'Method to simplify twin stage scanner OVL machine matching'20085,904,570'Method for polymer removal after etching'19995,639,342'Method of monitoring and controlling a silicon nitride etch step'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (20)· patent assignee history
1997–1999Based in Hsinchu, TW· patent location history
2008–2017Based in Yonghe City, TW· patent location history
2011–2016Patents assigned to LIU HENG-HSIN (14)· patent assignee history
2011–2015Patents assigned to LIN CHIN-HSIANG (8)· patent assignee history
2014–2020Patents assigned to IBM (8)· patent assignee history
2014–2020Based in New Taipei, TW· patent location history
2014–2020Based in Beijing, CN· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (22)· patent assignee history
2021Based in Dearborn, MI, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 22 | 2015–2020 |
| TAIWAN SEMICONDUCTOR MFG | 20 | 1997–2016 |
| LIU HENG-HSINself | 14 | 2011–2016 |
| IBM | 8 | 2014–2020 |
| LIN CHIN-HSIANG | 8 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Taipei, TW | 28 | 2014–2020 |
| Yonghe City, TW | 11 | 2008–2017 |
| Beijing, CN | 7 | 2014–2020 |
| Hsinchu, TW | 2 | 1997–1999 |
| Dearborn, MI, US | 1 | 2021 |