Inventor
Debashish BASU
Inventor
US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices44%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
PatentTitleYear
12,368,095Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization202511,652,045Via contact patterning method to increase edge placement error margin202311,211,324Via contact patterning method to increase edge placement error margin202111,145,541Conductive via and metal line end fabrication and structures resulting therefrom2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to INTEL CORP (4)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 4 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 4 | 2021–2025 |