Inventor
Dae-Gyu Park
Inventor
Poughquag, NY, US
Overview
Patents· 89 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices45%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H01LSemiconductor devices16%
H10BElectronic memory devices5%
C23CCoating metallic material3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%
PatentTitleYear
11,039,130Video encoding/decoding method and apparatus, and recording medium in which bit stream is stored20219,812,599'Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys'20179,711,416'Fin field effect transistor including a strained epitaxial semiconductor shell'20179,711,417'Fin field effect transistor including a strained epitaxial semiconductor shell'20179,679,775'Selective dopant junction for a group III-V semiconductor device'20179,590,054'Low temperature spacer for advanced semiconductor devices'20179,576,964'Integrated fin and strap structure for an access transistor of a trench capacitor'20179,564,505'Changing effective work function using ion implantation during dual work function metal gate integration'20179,564,444'Method of forming integrated fin and strap structure for an access transistor of a trench capacitor'20179,553,107'Shallow extension junction'20179,418,846'Selective dopant junction for a group III-V semiconductor device'20169,391,171'Fin field effect transistor including a strained epitaxial semiconductor shell'20169,349,650'Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs'20169,349,649'Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs'20169,318,318'3D atomic layer gate or junction extender'20169,306,038'Shallow extension junction'20169,293,557'Low temperature spacer for advanced semiconductor devices'20169,287,136'FinFET field-effect transistors with atomic layer doping'20169,275,907'3D transistor channel mobility enhancement'20169,236,314'High-K/metal gate stack using capping layer methods, IC and related transistors'20169,105,741'Method of replacement source/drain for 3D CMOS transistors'20159,099,585'Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys'20159,059,016'Lateral heterojunction bipolar transistors'20159,054,192'Integration of Ge-containing fins and compound semiconductor fins'20159,048,261'Fabrication of field-effect transistors with atomic layer doping'20159,034,748'Process variability tolerant hard mask for replacement metal gate finFET devices'20159,023,697'3D transistor channel mobility enhancement'20158,778,448'Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys'20148,753,936'Changing effective work function using ion implantation during dual work function metal gate integration'20148,748,252'Replacement metal gate transistors using bi-layer hardmask'20148,643,061'Structure of high-K metal gate semiconductor transistor'20148,637,381'High-k dielectric and silicon nitride box region'20148,586,441'Germanium lateral bipolar junction transistor'20138,580,635'Method of replacing silicon with metal in integrated circuit chip fabrication'20138,557,670'SOI lateral bipolar junction transistor having a wide band gap emitter contact'20138,557,652'Application of cluster beam implantation for fabricating threshold voltage adjusted FETs'20138,558,282'Germanium lateral bipolar junction transistor'20138,492,848'Application of cluster beam implantation for fabricating threshold voltage adjusted FETs'20138,445,969'High pressure deuterium treatment for semiconductor/high-K insulator interface'20138,421,191'Monolayer dopant embedded stressor for advanced CMOS'20138,410,544'finFETs and methods of making same'20138,299,535'Delta monolayer dopants epitaxy for embedded source/drain silicide'20128,288,222'Application of cluster beam implantation for fabricating threshold voltage adjusted FETs'20128,236,660'Monolayer dopant embedded stressor for advanced CMOS'20128,183,642'Gate effective-workfunction modification for CMOS'20128,106,462'Balancing NFET and PFET performance using straining layers'20128,088,663'SRAM cell having a rectangular combined active area planar pass gate and planar pull-down NFETS'20128,043,920'finFETS and methods of making same'20118,030,716'Self-aligned CMOS structure with dual workfunction'20117,989,298'Transistor having V-shaped embedded stressor'20117,947,549'Gate effective-workfunction modification for CMOS'20117,911,008'SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS'20117,893,502'Threshold voltage improvement employing fluorine implantation and adjustment oxide layer'20117,872,303'FinFET with longitudinal stress in a channel'20117,867,839'Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors'20117,863,126'Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region'20117,683,418'High-temperature stable gate structure with metallic electrode'20107,666,774'CMOS structure including dual metal containing composite gates'20107,611,979'Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks'20097,528,042'Method for fabricating semiconductor devices having dual gate oxide layer'20097,521,345'High-temperature stable gate structure with metallic electrode'20097,504,700'Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method'20097,504,696'CMOS with dual metal gate'20097,485,910'Simplified vertical array device DRAM/eDRAM integration: method and structure'20097,439,128'Method of creating deep trench capacitor using a P+ metal electrode'20087,282,403'Temperature stable metal nitride gate electrode'20077,279,413'High-temperature stable gate structure with metallic electrode'20077,157,359'Method of forming a metal gate in a semiconductor device using atomic layer deposition process'20077,157,339'Method for fabricating semiconductor devices having dual gate oxide layers'20077,084,024'Gate electrode forming methods using conductive hard mask'20067,023,064'Temperature stable metal nitride gate electrode'20066,967,137'Forming collar structures in deep trench capacitors with thermally stable filler material'20056,909,137'Method of creating deep trench capacitor using a P+ metal electrode'20056,828,185'CMOS of semiconductor device and method for manufacturing the same'20046,768,179'CMOS of semiconductor device and method for manufacturing the same'20046,664,160'Gate structure with high K dielectric'20036,642,132'Cmos of semiconductor device and method for manufacturing the same'20036,579,767'Method for forming aluminum oxide as a gate dielectric'20036,524,918'Method for manufacturing a gate structure incorporating therein aluminum oxide as a gate dielectric'20036,514,826'Method of forming a gate electrode in a semiconductor device'20036,511,875'Method for making high K dielectric gate for semiconductor device'20036,506,676'Method of manufacturing semiconductor devices with titanium aluminum nitride work function'20036,448,166'Method for forming a gate for semiconductor devices'20026,391,724'Method for manufacturing a gate structure incorporating aluminum oxide as a gate dielectric'20026,391,727'Method of manufacturing a semiconductor device utilizing a(Al2O3)X-(TiO2)1-X gate dielectric film'20026,355,548'Method for manufacturing a gate structure incorporated therein a high K dielectric'20026,323,083'Method for forming lower electrode structure of capacitor of semiconductor device'20016,171,941'Method for fabricating capacitor of semiconductor memory device using titanium aluminum nitride as diffusion-inhibiting layer'20015,919,281'2-stage fluidized bed furnace for pre-reducing fine iron ore and method for pre-reducing fine iron ore using the furnace'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2003Patents assigned to HYUNDAI ELECTRONICS IND (10)· patent assignee history
2001–2009Based in Kyungki-do, KR· patent location history
2002–2009Patents assigned to HYNIX SEMICONDUCTOR INC (8)· patent assignee history
2002–2004Based in Ichon-shi, KR· patent location history
2005–2017Patents assigned to IBM (63)· patent assignee history
2005–2010Based in Wappingers Falls, NY, US· patent location history
2009–2017Based in Poughquag, NY, US· patent location history
2011–2017Based in Poughquaq, NY, US· patent location history
2012–2016Patents assigned to PARK DAE-GYU (24)· patent assignee history
2012–2016Patents assigned to CHAN KEVIN K (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 63 | 2005–2017 |
| PARK DAE-GYUself | 24 | 2012–2016 |
| CHAN KEVIN K | 11 | 2012–2016 |
| HYUNDAI ELECTRONICS IND | 10 | 2001–2003 |
| HYNIX SEMICONDUCTOR INC | 8 | 2002–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughquag, New York, US | 27 | 2009–2017 |
| Poughquaq, New York, US | 24 | 2011–2017 |
| Wappingers Falls, New York, US | 11 | 2005–2010 |
| Kyungki-do, KR | 10 | 2001–2009 |
| Ichon-shi, KR | 8 | 2002–2004 |