Inventor

WEN-TING CHU

Inventor

TW

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 68 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices27%

H10NElectric solid-state devices not otherwise provided for23%

H01LSemiconductor devices18%

G11CStatic stores10%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H10DInorganic electric semiconductor devices9%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%

G06FElectric digital data processing1%

PatentTitleYear

12,593,458Semiconductor device2026 12,593,623RRAM with a barrier layer2026 12,588,429Resistive memory device including a silicon oxide base spacer and methods for forming the same2026 12,520,731Memory device2026 12,507,602RRAM with post-patterned treated memory films to provide improved endurance characteristics and methods for forming2025 12,389,814High electron affinity dielectric layer to improve cycling2025 12,356,875RRAM bottom electrode2025 12,336,442Memory device with bottom electrode2025 12,322,441Resistive random access memory device2025 12,322,429Embedded ferroelectric memory cell2025 12,256,652Metal landing on top electrode of RRAM2025 12,238,939Memory device having two memory stacks over one bottom electrode2025 12,232,333Integrated circuit2025 12,218,005Integrated circuit device2025 12,167,611FeRAM MFM structure with selective electrode etch2024 12,161,056Memory structure2024 12,156,409Memory layout for reduced line loading2024 12,082,421Semiconductor device and method for manufacturing the same2024 12,075,634RRAM memory cell with multiple filaments2024 12,069,971Switching layer scheme to enhance RRAM performance2024 12,057,154Method for efficiently waking up ferroelectric memory2024 12,041,861RRAM bottom electrode2024 12,040,019Methods for enlarging the memory window and improving data retention in resistive memory device2024 11,980,041Method to form memory cells separated by a void-free dielectric structure2024 11,944,021Metal landing on top electrode of RRAM2024 11,915,754Resistive random access memory device2024 11,894,267Method for fabricating integrated circuit device2024 11,889,705Interconnect landing method for RRAM technology2024 11,869,564Embedded ferroelectric memory cell2024 11,856,797Resistive switching random access memory with asymmetric source and drain2023 11,856,788Semiconductor device and method of fabricating the same2023 11,844,286Flat bottom electrode via (BEVA) top surface for memory2023 11,839,090Memory cells separated by a void-free dielectric structure2023 11,832,529Memory device2023 11,800,720Memory cell having a top electrode interconnect arranged laterally from a recess2023 11,785,777FeRAM MFM structure with selective electrode etch2023 11,751,405Integrated circuit and method for fabricating the same2023 11,751,485Flat bottom electrode via (BEVA) top surface for memory2023 11,737,290RRAM memory cell with multiple filaments2023 11,723,294Memory device and method for fabricating the same2023 11,723,292RRAM cell structure with laterally offset BEVA/TEVA2023 11,706,930Semiconductor device and method for manufacturing the same2023 11,696,521High electron affinity dielectric layer to improve cycling2023 11,683,999Switching layer scheme to enhance RRAM performance2023 11,682,456Methods for enlarging the memory window and improving data retention in restistive memory device2023 11,678,592Step height mitigation in resistive random access memory structures2023 11,678,494Memory layout for reduced line loading2023 11,637,239High yield RRAM cell with optimized film scheme2023 11,631,810Bottom electrode structure in memory device2023 11,611,038Method for forming RRAM with a barrier layer2023 11,557,344Resistive random access memory device2023 11,437,084Embedded ferroelectric memory cell2022 11,387,411Logic compatible RRAM structure and process2022 11,362,271Switching layer scheme to enhance RRAM performance2022 11,329,221Electrode structure to improve RRAM performance2022 11,316,096Memory device2022 11,315,861Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory2022 11,296,147Method for manufacturing memory device having spacer2022 11,276,819Metal landing on top electrode of RRAM2022 11,257,844Ferroelectric random access memory (FRAM) cell2022 11,239,279Resistive switching random access memory with asymmetric source and drain2022 11,227,872FeRAM MFM structure with selective electrode etch2022 11,201,190RRAM memory cell with multiple filaments2021 11,201,281Method for forming a flat bottom electrode via (BEVA) top surface for memory2021 11,195,840Method and structures pertaining to improved ferroelectric random-access memory (FeRAM)2021 11,189,788RRAM bottom electrode2021 11,183,503Memory cell having top and bottom electrodes defining recesses2021 11,183,631Electrode structure to improve RRAM performance2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (68)· patent assignee history

2021–2026Based in TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	68	2021–2026

Locations

Location	Patents	Span
TW	68	2021–2026