Inventor
Eyal Odiz
Inventor
Los Altos Hills, CA, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,643,012Concurrent formal verification of logic synthesis202010,372,858Design-for-testability (DFT) insertion at register-transfer-level (RTL)201910,354,032Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus20199,697,314'Identifying and using slices in an integrated circuit (IC) design'20179,690,890'Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design'20179,652,573'Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design'2017Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2017–2020Patents assigned to SYNOPSYS INC (6)· patent assignee history
2017–2019Based in Los Altos Hills, CA, US· patent location history
2020Based in Los Altos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SYNOPSYS INC | 6 | 2017–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos Hills, California, US | 5 | 2017–2019 |
| Los Altos, California, US | 1 | 2020 |