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Inventor

Chung-Li Wang

Inventor
San Jose, CA, US

Overview

47→
Patents
2013–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 47 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Mprimary
H03MCoding55%
G11BInformation storage based on relative movement between record carrier and transducer21%
G06FElectric digital data processing16%
G11CStatic stores4%
H04LTransmission of digital information, e.g. telegraphic communication4%
PatentTitleYear
10,715,182Systems and methods for decoding error correcting codes with self-generated LLR202010,574,274Systems and methods for decoding error correcting codes202010,511,326Systems and methods for decoding error correcting codes201910,491,244Systems and methods for decoding error correcting codes201910,141,072Efficient encoder based on modified RU algorithm201810,135,464Reliability-assisted bit-flipping decoding algorithm20189,996,285Cyclically interleaved XOR array for error recovery20189,906,240'One-shot decoder for two-error-correcting BCH codes'20189,866,241'Techniques for adaptive LDPC decoding'20189,710,326'Encoder by-pass with scrambler'20179,324,372'Systems and methods for local iteration randomization in a data decoder'20169,244,685'System and method for check-node unit message processing'20169,214,959'Systems and methods for skip layer data decoding'20159,130,589'Low density parity check decoder with dynamic scaling'20159,130,590'Non-binary layered low density parity check decoder'20159,058,842'Systems and methods for gate aware iterative data processing'20159,048,873'Systems and methods for multi-stage encoding of concatenated low density parity check codes'20159,048,874'Min-sum based hybrid non-binary low density parity check decoder'20159,048,867'Shift register-based layered low density parity check decoder'20159,037,938'Hardware architecture and implementation of low power layered multi-level LDPC decoder'20159,037,952'Memory architecture for layered low-density parity-check decoder'20159,015,550'Low density parity check layer decoder for codes with overlapped circulants'20159,015,547'Multi-level LDPC layered decoder with out-of-order processing'20159,009,557'Systems and methods for reusing a layered decoder to yield a non-layered result'20158,977,926'Modified targeted symbol flipping for non-binary LDPC codes'20158,977,937'Systems and methods for compression driven variable rate decoding in a data processing system'20158,977,924'Optimized mechanism to simplify the circulant shifter and the P/Q kick out for layered LDPC decoder'20158,959,414'Systems and methods for hybrid layer data decoding'20158,949,696'Systems and methods for trapping set disruption'20158,949,704'Systems and methods for mis-correction correction in a data processing system'20158,947,804'Systems and methods for combined binary and non-binary data processing'20158,929,009'Irregular low density parity check decoder with low syndrome error handling'20158,885,276'Systems and methods for shared layer data decoding'20148,856,575'Systems and methods for power measurement in a data processing system'20148,782,488'Systems and methods for back step data decoding'20148,782,487'Systems and methods for locating and correcting decoder mis-corrections'20148,775,896'Non-binary LDPC decoder with low latency scheduling'20148,775,897'Data processing system with failure recovery'20148,756,478'Multi-level LDPC layer decoder'20148,751,913'Systems and methods for reduced power multi-layer data decoding'20148,707,144'LDPC decoder with targeted symbol flipping'20148,661,324'Systems and methods for non-binary decoding biasing control'20148,566,666'Min-sum based non-binary LDPC decoder'20138,560,929'Systems and methods for non-binary decoding'20138,560,930'Systems and methods for multi-level quasi-cyclic low density parity check codes'20138,525,707'Systems and methods for dual binary and non-binary decoding processing'20138,499,231'Systems and methods for reduced format non-binary decoding'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2016Patents assigned to LSI CORP (36)· patent assignee history
2013–2016Patents assigned to WANG CHUNG-LI (21)· patent assignee history
2013–2016Patents assigned to YANG SHAOHUA (17)· patent assignee history
2013–2015Patents assigned to LI ZONGWANG (13)· patent assignee history
2013–2016Patents assigned to HAN YANG (10)· patent assignee history
2013–2016Based in San Jose, CA, US· patent location history
2017–2020Based in Fremont, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI CORP362013–2016
WANG CHUNG-LIself212013–2016
YANG SHAOHUA172013–2016
LI ZONGWANG132013–2015
HAN YANG102013–2016
Locations
LocationPatentsSpan
San Jose, California, US372013–2016
Fremont, California, US102017–2020