Inventor
Dong Chen
Inventor
Croton-on-Hudson, NY, US
Overview
Patents· 98 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing34%
H04LTransmission of digital information, e.g. telegraphic communication19%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications8%
F04DNon-positive-displacement pumps8%
F24FAir-conditioning8%
G09GArrangements or circuits for control of indicating devices using static means to present variable information8%
H05KPrinted circuits8%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H03MCoding3%
G11BInformation storage based on relative movement between record carrier and transducer0%
PatentTitleYear
10,834,672Power management of network links202010,812,416Reduced number of counters for reliable messaging202010,740,097Embedding global barrier and collective in a torus network202010,601,697I/O routing in a multidimensional torus network202010,425,358Network switch architecture supporting multiple simultaneous collective operations201910,348,609I/O routing in a multidimensional torus network201910,152,450Remote processing and memory utilization201810,140,179Combined group ECC protection and subgroup parity protection201810,069,599Collective network for computer structures20189,971,713Multi-petascale highly efficient parallel supercomputer20189,954,760I/O routing in a multidimensional torus network20189,948,543Mechanism to extend the remote get to do async rectangle broadcast on a rectangle with wild cards in the packet header20189,893,950'Switch-connected HyperX network'20189,699,078'Multi-planed unified switching topologies'20179,565,094'I/O routing in a multidimensional torus network'20179,507,647'Cache as point of coherence in multiprocessor system'20169,501,333'Multiprocessor system with multiple concurrent modes of execution'20169,495,131'Multi-input and binary reproducible, high bandwidth floating point adder in a collective network'20169,374,414'Embedding global and collective in a torus network with message class map based tree path selection'20169,252,814'Combined group ECC protection and subgroup parity protection'20169,244,759'Error recovery to enable error-free message transfer between nodes of a computer network'20169,137,098'T-Star interconnection network topology'20159,081,501'Multi-petascale highly efficient parallel supercomputer'20159,077,616'T-star interconnection network topology'20159,037,669'Remote processing and memory utilization'20158,977,669'Multi-input and binary reproducible, high bandwidth floating point adder in a collective network'20158,943,350'Synchronizing compute node time bases in a parallel computer'20158,943,199'Calculating a checksum with inactive networking components in a computing system'20158,924,763'Synchronizing compute node time bases in a parallel computer'20148,914,498'Calculating a checksum with inactive networking components in a computing system'20148,892,824'Store-operate-coherence-on-value'20148,856,490'Optimizing TLB entries for mixed page size storage in contiguous memory'20148,856,261'Network support for system initiated checkpoints'20148,838,944'Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives'20148,788,879'Non-volatile memory for checkpoint storage'20148,782,164'Implementing asyncronous collective operations in a multi-node processing system'20148,756,350'Method and apparatus for efficiently tracking queue entries relative to a timestamp'20148,667,049'Massively parallel supercomputer'20148,631,086'Preventing messaging queue deadlocks in a DMA environment'20148,626,957'Collective network for computer structures'20148,621,478'Multiprocessor system with multiple concurrent modes of execution'20138,595,554'Reproducibility in a multiprocessor system'20138,521,990'Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders'20138,509,255'Hardware packet pacing using a DMA in a parallel computer'20138,468,416'Combined group ECC protection and subgroup parity protection'20138,458,267'Distributed parallel messaging for multiprocessor systems'20138,458,282'Extended write combining using a write continuation hint flag'20138,447,960'Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition'20138,429,377'Optimizing TLB entries for mixed page size storage in contiguous memory'20138,412,974'Global synchronization of parallel processors using clock pulse width modulation'20138,364,844'Deadlock-free class routes for collective communications embedded in a multi-dimensional torus network'20138,359,404'Zone routing in a torus network'20138,359,367'Network support for system initiated checkpoints'20138,255,638'Snoop filter for filtering snoop requests'20128,250,133'Massively parallel supercomputer'20128,161,248'Simplifying and speeding the management of intra-node cache coherence'20128,122,197'Managing coherence via put/get windows'20128,112,559'Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment'20128,103,836'Snoop filtering system in a multiprocessor system'20128,103,910'Local rollback for fault-tolerance in parallel computing systems'20128,095,585'Efficient implementation of multidimensional fast fourier transform on a distributed-memory parallel multi-node computer'20128,086,766'Support for non-locking parallel reception of packets belonging to a single memory reception FIFO'20118,032,892'Message passing with a limited number of DMA byte counters'20118,010,875'Error correcting code with chip kill capability and power saving enhancement'20118,001,280'Collective network for computer structures'20117,886,084'Optimized collectives using a DMA on a parallel computer'20117,870,343'Managing coherence via put/get windows'20117,817,585'Data capture technique for high speed signaling'20107,818,514'Low latency memory access and synchronization'20107,802,025'DMA engine for repeating communication patterns'20107,793,038'System and method for programmable bank selection for banked memory subsystems'20107,788,334'Multiple node remote messaging'20107,765,337'Direct memory access transfer completion notification'20107,761,687'Ultrascalable petaflop parallel supercomputer'20107,701,846'Bad data packet capture device'20107,694,035'DMA shared byte counters in a parallel computer'20107,668,970'Optimized scalable network switch'20107,650,434'Global tree network for computing structures enabling global processing operations'20107,620,841'Re-utilizing partially failed resources as network resources'20097,603,523'Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture'20097,587,516'Class network routing'20097,555,566'Massively parallel supercomputer'20097,529,895'Method for prefetching non-contiguous data structures'20097,486,619'Multidimensional switch network'20097,457,303'One-bounce network'20087,444,385'Global interrupt and barrier networks'20087,418,068'Data capture technique for high speed signaling'20087,386,683'Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture'20087,383,490'Methods and apparatus using commutative error detection values for fault isolation in multiple node computers'20087,380,071'Snoop filtering system in a multiprocessor system'20087,373,462'Snoop filter for filtering snoop requests'20087,315,877'Efficient implementation of a multidimensional fast fourier transform on a distributed-memory parallel multi-node computer'20087,313,582'Arithmetic functions in torus and tree networks'20077,305,487'Optimized scalable network switch'20077,210,088'Fault isolation through no-overhead link level CRC'20077,185,226'Fault tolerance in a supercomputer through dynamic repartitioning'20077,174,434'Low latency memory access and synchronization'20077,149,920'Deterministic error recovery protocol'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2020Patents assigned to IBM (96)· patent assignee history
2006–2020Based in Croton-on-Hudson, NY, US· patent location history
2011–2018Patents assigned to CHEN DONG (41)· patent assignee history
2011–2018Patents assigned to HEIDELBERGER PHILIP (35)· patent assignee history
2011–2016Patents assigned to STEINMACHER-BUROW BURKHARD (16)· patent assignee history
2011–2018Based in Yorktown Heights, NY, US· patent location history
2012–2016Patents assigned to OHMACHT MARTIN (19)· patent assignee history
2017–2020Based in Scarsdale, NY, US· patent location history
2019Based in Scardale, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 96 | 2006–2020 |
| CHEN DONGself | 41 | 2011–2018 |
| HEIDELBERGER PHILIP | 35 | 2011–2018 |
| OHMACHT MARTIN | 19 | 2012–2016 |
| STEINMACHER-BUROW BURKHARD | 16 | 2011–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Croton-on-Hudson, New York, US | 73 | 2006–2020 |
| Yorktown Heights, New York, US | 18 | 2011–2018 |
| Scarsdale, New York, US | 6 | 2017–2020 |
| Scardale, New York, US | 1 | 2019 |