Inventor

Roger A. Golliver

Inventor

Beaverton, OR, US

Overview

1999–2020

Patent span

Physics

Primary field (CPC G)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing94%

H04LTransmission of digital information, e.g. telegraphic communication4%

H03MCoding2%

PatentTitleYear

10,649,662Methods and apparatus to manage workload memory allocation2020 10,067,680Methods and apparatus to manage workload memory allocation2018 9,823,850'Methods and apparatus to manage workload memory allocation'2017 9,612,951'Methods and apparatus to manage workload memory allocation'2017 9,513,976'Providing extended memory semantics with atomic memory operations'2016 9,361,217'Methods and apparatus to manage workload memory allocation'2016 9,141,386'Vector logical reduction operation implemented using swizzling on a semiconductor chip'2015 9,092,213'Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation'2015 8,996,765'Methods and apparatus to manage workload memory allocation'2015 8,667,042'Functional unit for vector integer multiply add instruction'2014 7,380,278'Protecting software environment in isolated execution'2008 7,254,707'Platform and method for remote attestation of a platform'2007 7,194,634'Attestation key memory device and bus'2007 7,111,176'Generating isolated bus cycles for isolated execution'2006 7,096,497'File checking using remote signing authority via a network'2006 7,089,418'Managing accesses in a processor for isolated execution'2006 7,085,935'Managing a secure environment using a chipset in isolated execution mode'2006 7,082,615'Protecting software environment in isolated execution'2006 7,073,071'Platform and method for generating and utilizing a protected audit log'2006 7,013,481'Attestation key memory device and bus'2006 7,013,484'Managing a secure environment using a chipset in isolated execution mode'2006 6,996,710'Platform and method for issuing and certifying a hardware-protected attestation key'2006 6,990,579'Platform and method for remote attestation of a platform'2006 6,957,332'Managing a secure platform using a hierarchical executive architecture in isolated execution mode'2005 6,941,458'Managing a secure platform using a hierarchical executive architecture in isolated execution mode'2005 6,934,817'Controlling access to multiple memory zones in an isolated execution environment'2005 6,795,905'Controlling accesses to isolated memory using a memory controller for isolated execution'2004 6,769,058'Resetting a processor in an isolated execution environment'2004 6,760,441'Generating a key hieararchy for use in an isolated execution environment'2004 6,754,815'Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set'2004 6,678,825'Controlling access to multiple isolated memories in an isolated execution environment'2004 6,633,963'Controlling access to multiple memory zones in an isolated execution environment'2003 6,578,059'Methods and apparatus for controlling exponent range in floating-point calculations'2003 6,507,904'Executing isolated mode instructions in a secure system running in privilege rings'2003 6,502,117'Data manipulation instruction for enhancing value and efficiency of complex arithmetic'2002 6,378,067'Exception reporting architecture for SIMD-FP instructions'2002 6,370,639'Processor architecture having two or more floating-point status fields'2002 6,321,327'Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations'2001 6,292,886'Scalar hardware for performing SIMD operations'2001 6,272,512'Data manipulation instruction for enhancing value and efficiency of complex arithmetic'2001 6,249,798'Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit'2001 6,243,734'Computer product and method for sparse matrices'2001 6,212,539'Methods and apparatus for handling and storing bi-endian words in a floating-point processor'2001 6,212,627'System for converting packed integer data into packed floating point data in reduced time'2001 6,185,670'System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields'2001 6,151,669'Methods and apparatus for efficient control of floating-point status register'2000 6,105,047'Method and apparatus for trading performance for precision when processing denormal numbers in a computer system'2000 6,073,210'Synchronization of weakly ordered write combining operations using a fencing mechanism'2000 6,009,263'Emulating agent and method for reformatting computer instructions into a standard uniform format'1999 5,928,356'Method and apparatus for selectively controlling groups of registers'1999 5,886,915'Method and apparatus for trading performance for precision when processing denormal numbers in a computer system'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2020Patents assigned to INTEL CORP (43)· patent assignee history

1999–2003Patents assigned to INST THE DEV OF EMERGING ARCHI (7)· patent assignee history

1999–2020Based in Beaverton, OR, US· patent location history

2014–2016Patents assigned to GOLLIVER ROGER (5)· patent assignee history

2014–2015Patents assigned to SAMUDRALA SRIDHAR (3)· patent assignee history

2014–2015Patents assigned to WIEDEMEIER JEFF (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	43	1999–2020
INST THE DEV OF EMERGING ARCHI	7	1999–2003
GOLLIVER ROGERself	5	2014–2016
SAMUDRALA SRIDHAR	3	2014–2015
WIEDEMEIER JEFF	3	2014–2015

Locations

Location	Patents	Span
Beaverton, OR, US	51	1999–2020