Inventor

Sanjay C. Mehta

Inventor

Niskayuna, NY, US

Overview

2007–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 113 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices27%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

H10BElectronic memory devices3%

C23CCoating metallic material2%

B82YSpecific uses or applications of nanostructures1%

H01BCables1%

Y10TTechnical subjects covered by former us classification1%

PatentTitleYear

10,879,375Gate tie-down enablement with inner spacer2020 10,840,354Approach to bottom dielectric isolation for vertical transport fin field effect transistors2020 10,784,258Selective contact etch for unmerged epitaxial source/drain regions2020 10,784,371Self aligned top extension formation for vertical transistors2020 10,707,326Vertical field-effect-transistors having a silicon oxide layer with controlled thickness2020 10,692,985Protection of high-K dielectric during reliability anneal on nanosheet structures2020 10,651,308Self aligned top extension formation for vertical transistors2020 10,629,702Approach to bottom dielectric isolation for vertical transport fin field effect transistors2020 10,580,855High thermal budget compatible punch through stop integration using doped glass2020 10,580,854High thermal budget compatible punch through stop integration using doped glass2020 10,529,828Method of forming vertical transistor having dual bottom spacers2020 10,522,654Gate tie-down enablement with inner spacer2019 10,418,277Air gap spacer formation for nano-scale semiconductor devices2019 10,366,988Selective contact etch for unmerged epitaxial source/drain regions2019 10,355,109Spacer formation on semiconductor device2019 10,332,977Gate tie-down enablement with inner spacer2019 10,304,936Protection of high-K dielectric during reliability anneal on nanosheet structures2019 10,269,652Vertical transistor top epitaxy source/drain and contact structure2019 10,262,904Vertical transistor top epitaxy source/drain and contact structure2019 10,256,320Vertical field-effect-transistors having a silicon oxide layer with controlled thickness2019 10,236,360Method of forming vertical transistor having dual bottom spacers2019 10,229,982Pure boron for silicide contact2019 10,170,479Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors2019 10,128,352Gate tie-down enablement with inner spacer2018 10,115,629Air gap spacer formation for nano-scale semiconductor devices2018 10,079,299Self aligned top extension formation for vertical transistors2018 10,056,382Modulating transistor performance2018 10,014,299Field effect transistor device spacers2018 9,985,096High thermal budget compatible punch through stop integration using doped glass2018 9,954,103Bottom spacer formation for vertical transistor2018 9,953,976Effective device formation for advanced technology nodes with aggressive fin-pitch scaling2018 9,941,163Gate tie-down enablement with inner spacer2018 9,941,391Method of forming vertical transistor having dual bottom spacers2018 9,929,049'Gate tie-down enablement with inner spacer'2018 9,923,074'Pure boron for silicide contact'2018 9,911,831'Spacer formation on semiconductor device'2018 9,911,823'POC process flow for conformal recess fill'2018 9,899,259'Gate tie-down enablement with inner spacer'2018 9,892,961'Air gap spacer formation for nano-scale semiconductor devices'2018 9,876,091Divot-free planarization dielectric layer for replacement gate2018 9,871,041'Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors'2018 9,847,388High thermal budget compatible punch through stop integration using doped glass2017 9,773,901'Bottom spacer formation for vertical transistor'2017 9,748,359'Vertical transistor bottom spacer formation'2017 9,748,382'Self aligned top extension formation for vertical transistors'2017 9,741,813'Pure boron for silicide contact'2017 9,735,054'Gate tie-down enablement with inner spacer'2017 9,735,248'Pure boron for silicide contact'2017 9,653,573'Replacement metal gate including dielectric gate material'2017 9,640,514'Wafer bonding using boron and nitrogen based bonding stack'2017 9,634,110'POC process flow for conformal recess fill'2017 9,627,257'Gate tie-down enablement with inner spacer'2017 9,607,825'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'2017 9,583,489'Solid state diffusion doping for bulk finFET devices'2017 9,576,954'POC process flow for conformal recess fill'2017 9,564,370'Effective device formation for advanced technology nodes with aggressive fin-pitch scaling'2017 9,558,934'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'2017 9,558,935'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'2017 9,536,981'Field effect transistor device spacers'2017 9,536,733'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'2017 9,530,651'Replacement metal gate finFET'2016 9,484,431'Pure boron for silicide contact'2016 9,484,256'Pure boron for silicide contact'2016 9,472,407'Replacement metal gate FinFET'2016 9,449,812'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'2016 9,443,855'Spacer formation on semiconductor device'2016 9,437,436'Replacement metal gate FinFET'2016 9,425,292'Field effect transistor device spacers'2016 9,406,767'POC process flow for conformal recess fill'2016 9,397,049'Gate tie-down enablement with inner spacer'2016 9,373,697'Spacer replacement for replacement metal gate semiconductor devices'2016 9,356,121'Divot-free planarization dielectric layer for replacement gate'2016 9,318,347'Wafer backside particle mitigation'2016 9,245,965'Uniform finFET gate height'2016 9,236,397'FinFET device containing a composite spacer structure'2016 9,209,126'Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication'2015 9,184,042'Wafer backside particle mitigation'2015 9,171,927'Spacer replacement for replacement metal gate semiconductor devices'2015 9,166,049'Method to enhance strain in fully isolated finFET structures'2015 9,153,447'Replacement metal gate FinFET'2015 9,093,376'Replacement metal gate FinFET'2015 9,054,127'Robust replacement gate integration'2015 8,927,387'Robust isolation for thin-box ETSOI MOSFETS'2015 8,912,612'Silicon nitride gate encapsulation by implantation'2014 8,906,759'Silicon nitride gate encapsulation by implantation'2014 8,900,973'Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion'2014 8,890,255'Structure and method for stress latching in non-planar semiconductor devices'2014 8,835,237'Robust replacement gate integration'2014 8,829,617'Uniform finFET gate height'2014 8,822,137'Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication'2014 8,790,991'Method and structure for shallow trench isolation to mitigate active shorts'2014 8,679,941'Method to improve wet etch budget in FEOL integration'2014 8,652,950'C-rich carbon boron nitride dielectric films for use in electronic devices'2014 8,617,961'Post-gate isolation area formation for fin field effect transistor device'2013 8,614,486'Low resistance source and drain extensions for ETSOI'2013 8,551,872'Low series resistance transistor structure on silicon on insulator layer'2013 8,535,999'Stress memorization process improvement for improved technology performance'2013 8,486,778'Low resistance source and drain extensions for ETSOI'2013 8,476,743'C-rich carbon boron nitride dielectric films for use in electronic devices'2013 8,440,552'Method to form low series resistance transistor devices on silicon on insulator layer'2013 8,394,684'Structure and method for stress latching in non-planar semiconductor devices'2013 8,372,705'Fabrication of CMOS transistors having differentially stressed spacers'2013 8,232,179'Method to improve wet etch budget in FEOL integration'2012 7,948,083'Reliable BEOL integration process with direct CMP of porous SiCOH dielectric'2011 7,855,428'Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer'2010 7,838,428'Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species'2010 7,816,253'Surface treatment of inter-layer dielectric'2010 7,704,854'Method for fabricating semiconductor device having conductive liner for rad hard total dose immunity'2010 7,517,736'Structure and method of chemically formed anchored metallic vias'2009 7,485,582'Hardmask for improved reliability of silicon based dielectrics'2009 7,335,980'Hardmask for reliability of silicon based dielectrics'2008 7,294,565'Method of fabricating a wire bond pad with Ni/Au metallization'2007 7,253,105'Reliable BEOL integration process with direct CMP of porous SiCOH dielectric'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2020Patents assigned to IBM (108)· patent assignee history

2007–2011Based in Poughkeepsie, NY, US· patent location history

2010–2020Based in Niskayuna, NY, US· patent location history

2010Based in Slingerlands, NY, US· patent location history

2012–2015Patents assigned to MEHTA SANJAY (13)· patent assignee history

2012–2015Patents assigned to HARAN BALASUBRAMANIAN S (9)· patent assignee history

2012–2014Patents assigned to JAGANNATHAN HEMANTH (6)· patent assignee history

2012–2014Based in Albany, NY, US· patent location history

2014–2020Patents assigned to GLOBALFOUNDRIES INC (25)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	108	2007–2020
GLOBALFOUNDRIES INC	25	2014–2020
MEHTA SANJAYself	13	2012–2015
HARAN BALASUBRAMANIAN S	9	2012–2015
JAGANNATHAN HEMANTH	6	2012–2014

Locations

Location	Patents	Span
Niskayuna, New York, US	103	2010–2020
Poughkeepsie, New York, US	6	2007–2011
Albany, New York, US	3	2012–2014
Slingerlands, New York, US	1	2010