Inventor
Ranjan J. Mathew
Inventor
San Jose, CA, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1041%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein14%
H05KPrinted circuits10%
Y10TTechnical subjects covered by former us classification8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems3%
H04NPictorial communication, e.g. television3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
C23CCoating metallic material2%
PatentTitleYear
7,880,310'Direct device attachment on dual-mode wirebond die'20117,262,513'Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon'20077,102,703'Liquid crystal display assembly for reducing optical defects'20066,927,156'Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon'20056,556,269'Connection assembly for reflective liquid crystal display and method'20036,498,636'Apparatus and method for substantially stress-free electrical connection to a liquid crystal display'20026,476,885'Stress-free socketed optical display package with die non-rigidly attached to containment structure'20026,459,143'Method of packaging fuses'20026,384,890'Connection assembly for reflective liquid crystal projection with branched PCB display'20026,357,763'Seal for LCD devices and methods for making same'20026,356,334'Liquid crystal display assembly and method for reducing residual stresses'20026,284,566'Chip scale package and method for manufacture thereof'20016,255,141'Method of packaging fuses'20016,140,708'Chip scale package and method for manufacture thereof'20006,122,033'Fusible seal for LCD devices and methods for making same'20006,054,338'Low cost ball grid array device and method of manufacture thereof'20005,969,783'Reflective liquid crystal display and connection assembly and method'19995,923,995'Methods and apparatuses for singulation of microelectromechanical systems'19995,832,585'Method of separating micro-devices formed on a substrate'19985,804,880'Solder isolating lead frame'19985,783,866'Low cost ball grid array device and method of manufacture thereof'19985,728,285'Protective coating combination for lead frames'19985,650,661'Protective coating combination for lead frames'19975,596,225'Leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die'19975,436,082'Protective coating combination for lead frames'19955,328,079'Method of and arrangement for bond wire connecting together certain integrated circuit components'19945,270,262'O-ring package'19935,208,186'Process for reflow bonding of bumps in IC devices'19934,963,233'Glass conditioning for ceramic package plating'19904,922,322'Bump structure for reflow bonding of IC devices'19904,800,178'Method of electroplating a copper lead frame with copper'19894,714,517'Copper cleaning and passivating for tape automated bonding'19874,589,962'Solder plating process and semiconductor product'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2006Patents assigned to NAT SEMICONDUCTOR CORP (30)· patent assignee history
1986–2011Based in San Jose, CA, US· patent location history
2005–2011Patents assigned to INTEL CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 30 | 1986–2006 |
| INTEL CORP | 3 | 2005–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 33 | 1986–2011 |