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Inventor

Raymond J. Beffa

Inventor
Boise, ID, US

Overview

58→
Patents
1998–2012
Patent span
Physics
Primary field (CPC G)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary
G01RMeasuring electric variables31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
B07CPostal sorting10%
G06FElectric digital data processing9%
G11CStatic stores9%
H10BElectronic memory devices4%
PatentTitleYear
8,189,423'256 Meg dynamic random access memory'20127,969,810'256 Meg dynamic random access memory'20117,885,782'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture'20117,875,821'Method for sorting integrated circuit devices'20117,682,847'Method for sorting integrated circuit devices'20107,567,091'Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20097,502,659'Sorting a group of integrated circuit devices for those devices requiring special testing'20097,489,564'256 Meg dynamic random access memory'20097,477,556'256 Meg dynamic random access memory'20097,477,557'256 Meg dynamic random access memory'20097,446,277'Method for sorting integrated circuit devices'20087,368,678'Method for sorting integrated circuit devices'20087,323,896'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20087,315,179'System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20087,276,927'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20077,276,672'Method for sorting integrated circuit devices'20077,276,926'Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20077,212,020'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20077,124,050'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC\'s mis-processed during their manufacture'20067,117,063'Sorting a group of integrated circuit devices for those devices requiring special testing'20067,107,117'Sorting a group of integrated circuit devices for those devices requiring special testing'20067,034,561'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20066,944,567'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture'20056,852,999'Reduced terminal testing system'20056,831,475'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20046,815,968'Reduced terminal testing system'20046,788,993'Sorting a group of integrated circuit devices for those devices requiring special testing'20046,703,573'Method for sorting integrated circuit devices'20046,636,068'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20036,594,611'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC\'s mis-processed during their manufacture'20036,534,785'Reduced terminal testing system'20036,529,793'Method of sorting a group of integrated circuit devices for those devices requiring special testing'20036,504,123'Process for sorting integrated circuit devices'20036,452,415'Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer'20026,437,271'Method for sorting integrated circuit devices'20026,424,168'Reduced terminal testing system'20026,373,011'Method for sorting integrated circuit devices'20026,365,860'Method for sorting integrated circuit devices'20026,365,861'Method for sorting integrated circuit devices'20026,363,329'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC\'s mis-processed during their manufacture'20026,350,959'Method for sorting integrated circuit devices'20026,324,088'256 meg dynamic random access memory'20016,313,658'Device and method for isolating a short-circuited integrated circuit (IC) from other IC\'s on a semiconductor wafer'20016,314,011'256 Meg dynamic random access memory'20016,307,171'Method for sorting integrated circuit devices'20016,292,009'Reduced terminal testing system'20016,208,947'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC\'s mis-processed during their manufacture'20016,147,316'Method for sorting integrated circuit devices'20006,122,563'Method of sorting a group of integrated circuit devices for those devices requiring special testing'20006,118,138'Reduced terminal testing system'20006,100,486'Method for sorting integrated circuit devices'20006,067,507'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC\'s mis-processd during their manufacture'20005,994,915'Reduced terminal testing system'19995,976,899'Reduced terminal testing system'19995,927,512'Method for sorting integrated circuit devices'19995,915,231'Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC\'s mis-processed during their manufacture'19995,898,186'Reduced terminal testing system'19995,844,803'Method of sorting a group of integrated circuit devices for those devices requiring special testing'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2011Patents assigned to MICRON TECHNOLOGY INC (56)· patent assignee history
1998–2012Based in Boise, ID, US· patent location history
2011–2012Patents assigned to ROUND ROCK RES LLC (2)· patent assignee history
2012Patents assigned to BEFFA RAYMOND J (1)· patent assignee history
2012Patents assigned to BUNKER LAYNE G (1)· patent assignee history
2012Patents assigned to KEETH BRENT (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC561998–2011
ROUND ROCK RES LLC22011–2012
BEFFA RAYMOND Jself12012
BUNKER LAYNE G12012
KEETH BRENT12012
Locations
LocationPatentsSpan
Boise, ID, US581998–2012