LexDanaLexDanabeta
Inventor

David R. Resnick

Inventor
Boise, ID, US

Overview

57→
Patents
1977–2020
Patent span
Physics
Primary field (CPC G)

Patents· 57 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing44%
G11CStatic stores28%
H03MCoding9%
G01RMeasuring electric variables6%
H03KPulse technique3%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G07FCoin-freed or like apparatus2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
H01LSemiconductor devices1%
PatentTitleYear
10,681,136Memory network methods, apparatus, and systems202010,490,277Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same201910,026,458Memories and methods for performing vector atomic memory operations with mask control and variable data length and data unit size201810,019,310Error correction in multiple semiconductor memory units20189,959,929Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same20189,424,891'Methods and devices for temperature sensing of a memory device'20169,348,785'Flexible and expandable memory architectures'20169,235,459'Failure recovery memory devices and methods'20169,071,273'Extended single-bit error correction and multiple-bit error detection'20159,032,145'Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same'20159,021,176'Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same'20159,009,556'Error correction and recovery in chained memory architectures'20158,977,822'Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same'20158,958,260'Systems and methods for voltage sensing and reporting'20158,892,985'Decoding and optimized implementation of SECDED codes over GF(q)'20148,799,743'Error correction in multiple semiconductor memory units'20148,756,484'Design, decoding and optimized implementation of SECDED codes over GF(q)'20148,732,533'Devices, methods, and apparatuses for detection, sensing, and reporting functionality for semiconductor memory'20148,707,092'Failure recovery memory devices and methods'20148,667,358'Error correction and recovery in chained memory architectures'20148,656,082'Flexible and expandable memory architectures'20148,566,684'Decoding and optimized implementation of SECDED codes over GF(q)'20138,566,677'Extended single-bit error correction and multiple-bit error detection'20138,549,092'Memory network methods, apparatus, and systems'20138,395,958'Methods and apparatus for voltage sensing and reporting'20138,381,059'Error correction and recovery in chained memory architectures'20138,347,176'Method and apparatus for memory read-refresh, scrubbing and variable-rate refresh'20138,291,174'Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same'20128,230,305'Extended single-bit error correction and multiple-bit error detection'20128,180,974'System, apparatus, and method for modifying the order of memory accesses'20128,139,434'Methods and apparatus for voltage sensing and reporting'20128,126,674'Memory-daughter-card-testing method and apparatus'20128,086,530'Electronic payment system utilizing intermediary account'20118,055,852'Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same'20118,046,628'Failure recovery memory devices and methods'20118,028,198'Devices, methods, and apparatuses for detection, sensing, and reporting functionality for semiconductor memory'20118,024,638'Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh'20117,954,029'System, apparatus, and method for memory built-in self testing using microcode sequencers'20117,870,351'System, apparatus, and method for modifying the order of memory accesses'20117,826,996'Memory-daughter-card-testing apparatus and method'20107,822,911'Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same'20107,721,175'System, apparatus, and method for memory built-in self testing using microcode sequencers'20107,692,996'Method, system, and apparatus for voltage sensing and reporting'20107,676,728'Apparatus and method for memory asynchronous atomic read-correct-write operation'20107,565,593'Apparatus and method for memory bit-swapping-within-address-range circuit'20097,320,100'Apparatus and method for memory with bit swapping on the fly and testing'20087,292,950'Multiple error management mode memory module'20077,184,916'Apparatus and method for testing memory cards'20076,529,928'Floating-point adder performing floating-point and integer operations'20036,349,398'Method and apparatus for partial-scan built-in self test logic'20026,295,597'Apparatus and method for improved vector processing to support extended-length integer arithmetic'20016,185,545'Electronic payment system utilizing intermediary account'20015,396,641'Reconfigurable memory processor'19954,791,602'Soft programmable logic array'19884,701,920'Built-in self-test system for VLSI circuit chips'19874,027,293'Microcode program sequencer'19774,019,144'Conditional latch circuit'1977

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1977–1988Patents assigned to CONTROL DATA CORP (3)· patent assignee history
1977Based in Arden Hills, MN, US· patent location history
1995–2013Based in Eau Claire, WI, US· patent location history
2001–2013Patents assigned to CRAY INC (10)· patent assignee history
2001–2011Based in Portland, OR, US· patent location history
2009–2016Based in Tucson, AZ, US· patent location history
2010–2020Patents assigned to MICRON TECHNOLOGY INC (38)· patent assignee history
2010–2020Based in Boise, ID, US· patent location history
2011–2018Patents assigned to RESNICK DAVID (6)· patent assignee history
2012–2014Patents assigned to RESNICK DAVID R (14)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC382010–2020
RESNICK DAVID Rself142012–2014
CRAY INC102001–2013
RESNICK DAVIDself62011–2018
CONTROL DATA CORP31977–1988
Locations
LocationPatentsSpan
Boise, ID, US332010–2020
Tucson, AZ, US92009–2016
Eau Claire, WI, US81995–2013
Portland, OR, US22001–2011
Arden Hills, Minnesota, US21977