Inventor
Hun-Jan Tao
Inventor
Hsinchu, TW
Overview
Patents· 142 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1034%
H10DInorganic electric semiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H01JElectric discharge tubes or discharge lamps4%
H10BElectronic memory devices2%
H01LSemiconductor devices1%
C11DDetergent compositions1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
9,218,974'Sidewall free CESL for enlarging ILD gap-fill window'20158,999,834'Sidewall-free CESL for enlarging ILD gap-fill window'20158,970,015'Method for protecting a gate structure during contact formation'20158,658,525'Methods for a gate replacement process'20148,648,446'Method for protecting a gate structure during contact formation'20148,529,783'Method for backside polymer reduction in dry-etch process'20138,497,169'Method for protecting a gate structure during contact formation'20138,415,799'Dual damascene interconnect in hybrid dielectric'20138,384,159'Semiconductor devices and methods with bilayer dielectrics'20138,372,755'Multilayer hard mask'20138,367,563'Methods for a gate replacement process'20138,299,508'CMOS structure with multiple spacers'20128,283,222'Method to form a semiconductor device having gate dielectric layers of varying thickness'20128,202,776'Method for protecting a gate structure during contact formation'20128,148,270'Low K dielectric surface damage control'20128,110,490'Gate oxide leakage reduction'20128,008,143'Method to form a semiconductor device having gate dielectric layers of varying thicknesses'20117,947,591'Semiconductor devices with dual-metal gate structures and fabrication methods thereof'20117,939,396'Base oxide engineering for high-K gate stacks'20117,875,547'Contact hole structures and contact structures and fabrication methods thereof'20117,834,389'Triangular space element for semiconductor device'20107,824,990'Multi-metal-oxide high-K gate dielectrics'20107,732,878'MOS devices with continuous contact etch stop layer'20107,713,380'Method and apparatus for backside polymer reduction in dry-etch process'20107,709,392'Low K dielectric surface damage control'20107,629,275'Multiple-time flash anneal process'20097,598,176'Method for photoresist stripping and treatment of low-k dielectric material'20097,579,248'Resolving pattern-loading issues of SiGe stressor'20097,531,399'Semiconductor devices and methods with bilayer dielectrics'20097,465,634'Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures'20087,436,009'Via structures and trench structures and dual damascene structures'20087,429,769'Recessed channel field effect transistor (FET) device'20087,410,854'Method of making FUSI gate and resulting structure'20087,402,866'Backside contacts for MOS devices'20087,400,401'Measuring low dielectric constant film properties during processing'20087,390,753'In-situ plasma treatment of advanced resists in fine pattern definition'20087,378,713'Semiconductor devices with dual-metal gate structures and fabrication methods thereof'20087,373,941'Wet cleaning cavitation system and method to remove particulate wafer contamination'20087,354,524'Method and system for processing multi-layer films'20087,354,847'Method of trimming technology'20087,341,943'Post etch copper cleaning using dry plasma'20087,307,009'Phosphoric acid free process for polysilicon gate definition'20077,301,645'In-situ critical dimension measurement'20077,294,544'Method of making a metal-insulator-metal capacitor in the CMOS process'2007RE039913'Method to control gate CD'20077,276,417'Hybrid STI stressor with selective re-oxidation anneal'20077,271,448'Multiple gate field effect transistor structure'20077,265,060'Bi-level resist structure and fabrication method for contact holes on semiconductor substrates'20077,265,056'Method for forming novel BARC open for precision critical dimension control'20077,241,674'Method of forming silicided gate structure'20077,217,663'Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof'20077,208,331'Methods and structures for critical dimension and profile measurement'20077,172,933'Recessed polysilicon gate structure for a strained silicon MOSFET device'20077,148,114'Process for patterning high-k dielectric material'20067,141,460'Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers'20067,122,484'Process for removing organic materials during formation of a metal interconnect'20067,115,450'Approach to improve line end shortening including simultaneous trimming of photosensitive layer and hardmask'20067,115,526'Method for wet etching of high k thin film at low temperature'20067,109,085'Etching process to avoid polysilicon notching'20067,092,096'Optical scatterometry method of sidewall spacer analysis'20067,078,351'Photoresist intensive patterning and processing'20067,074,727'Process for improving dielectric properties in low-k organosilicate dielectric material'20067,067,391'Method to form a metal silicide gate device'20067,067,235'Bi-layer photoresist dry development and reactive ion etch method'20067,060,628'Method for fabricating a hard mask polysilicon gate'20067,037,849'Process for patterning high-k dielectric material'20067,033,518'Method and system for processing multi-layer films'20067,029,992'Low oxygen content photoresist stripping process for low dielectric constant materials'20067,022,610'Wet cleaning method to eliminate copper corrosion'20067,023,042'Method of forming a stacked capacitor structure with increased surface area for a DRAM device'20067,008,878'Plasma treatment and etching process for ultra-thin dielectric films'20067,008,866'Large-scale trimming for ultra-narrow gates'20066,974,730'Method for fabricating a recessed channel field effect transistor (FET) device'20056,969,688'Wet etchant composition and method for etching HfO2 and ZrO2'20056,914,007'In-situ discharge to avoid arcing during plasma etch processes'20056,878,639'Borderless interconnection process'20056,869,868'Method of fabricating a MOSFET device with metal containing gate structures'20056,867,084'Gate structure and method of forming the gate dielectric with mini-spacer'20056,864,193'Aqueous cleaning composition containing copper-specific corrosion inhibitor'20056,849,531'Phosphoric acid free process for polysilicon gate definition'20056,828,205'Method using wet etching to trim a critical dimension'20046,828,248'Method of pull back for forming shallow trench isolation'20046,821,880'Process of dual or single damascene utilizing separate etching and DCM apparati'20046,812,044'Advanced control for plasma process'20046,794,302'Dynamic feed forward temperature control to achieve CD etching uniformity'20046,794,230'Approach to improve line end shortening'20046,787,455'Bi-layer photoresist method for forming high resolution semiconductor features'20046,780,782'Bi-level resist structure and fabrication method for contact holes on semiconductor substrates'20046,777,340'Method of etching a silicon containing layer using multilayer masks'20046,764,903'Dual hard mask layer patterning method'20046,764,911'Multiple etch method for fabricating spacer layers'20046,720,132'Bi-layer photoresist dry development and reactive ion etch method'20046,706,591'Method of forming a stacked capacitor structure with increased surface area for a DRAM device'20046,706,640'Metal silicide etch resistant plasma etch method'20046,686,129'Partial photoresist etching'20046,656,796'Multiple etch method for fabricating split gate field effect transistor (FET) device'20036,630,398'Borderless contact with buffer layer'20036,620,631'Plasma etch method for forming patterned layer with enhanced critical dimension (CD) control'20036,524,938'Method for gate formation with improved spacer profile control'20036,503,848'Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window'20036,500,727'Silicon shallow trench etching with round top corner by photoresist-free process'20026,498,067'Integrated approach for controlling top dielectric loss during spacer etching'20026,497,993'In situ dry etching procedure to form a borderless contact hole'20026,479,403'Method to pattern polysilicon gates with high-k material gate dielectric'20026,472,335'Methods of adhesion promoter between low-K layer and underlying insulating layer'20026,444,566'Method of making borderless contact having a sion buffer layer'20026,440,863'Plasma etch method for forming patterned oxygen containing plasma etchable layer'20026,436,841'Selectivity oxide-to-oxynitride etch process using a fluorine containing gas, an inert gas and a weak oxidant'20026,410,424'Process flow to optimize profile of ultra small size photo resist free contact'20026,407,002'Partial resist free approach in contact etch to improve W-filling'20026,399,515'Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity'20026,399,483'Method for improving faceting effect in dual damascene process'20026,333,271'Multi-step plasma etch method for plasma etch processing a microelectronic layer'20016,331,480'Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material'20016,326,296'Method of forming dual damascene structure with improved contact/via edge integrity'20016,319,822'Process for forming an integrated contact or via'20016,265,317'Top corner rounding for shallow trench isolation'20016,242,350'Post gate etch cleaning process for self-aligned gate mosfets'20016,235,440'Method to control gate CD'20016,194,128'Method of dual damascene etching'20016,183,937'Post photodevelopment isotropic radiation treatment method for forming patterned photoresist layer with attenuated linewidth'20016,174,818'Method of patterning narrow gate electrode'20016,165,881'Method of forming salicide poly gate with thin gate oxide and ultra narrow gate width'20006,156,629'Method for patterning a polysilicon gate in deep submicron technology'20006,129,091'Method for cleaning silicon wafers with deep trenches'20006,130,167'Method of preventing corrosion of a metal structure exposed in a non-fully landed via'20006,043,163'HCL in overetch with hard mask to improve metal line etching profile'20006,040,248'Chemistry for etching organic low-k materials'20006,037,266'Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher'20006,025,273'Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask'20006,015,735'Method for forming a multi-anchor DRAM capacitor and capacitor formed'20006,015,757'Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer'20005,981,398'Hard mask method for forming chlorine containing plasma etched layer'19995,930,644'Method of forming a shallow trench isolation using oxide slope etching'19995,925,575'Dry etching endpoint procedure to protect against photolithographic misalignments'19995,904,566'Reactive ion etch method for forming vias through nitrogenated silicon oxide layers'19995,899,748'Method for anchoring via/contact in semiconductor devices and devices formed'19995,880,005'Method for forming a tapered profile insulator shape'19995,871,658'Optical emisson spectroscopy (OES) method for monitoring and controlling plasma etch process when forming patterned layers'19995,837,599'Wafer surface modification for improved electrostatic chucking efficiency'19985,694,207'Etch rate monitoring by optical emission spectroscopy'19975,348,841'Organic dye-in-polymer (DIP) medium for write-once-read-many (WORM) optical discs'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994Based in Taichung, TW· patent location history
1997–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (138)· patent assignee history
1997–2015Based in Hsinchu, TW· patent location history
2003–2012Based in Hsin Chu, TW· patent location history
2004Based in Hsinchu County, TW· patent location history
2006–2013Patents assigned to TAO HUN-JAN (12)· patent assignee history
2012–2013Patents assigned to LEE DA-YUAN (3)· patent assignee history
2012–2013Patents assigned to CHANG HONG-DYI (2)· patent assignee history
2012–2013Patents assigned to CHUANG HARRY HAK-LAY (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 138 | 1997–2015 |
| TAO HUN-JANself | 12 | 2006–2013 |
| LEE DA-YUAN | 3 | 2012–2013 |
| CHANG HONG-DYI | 2 | 2012–2013 |
| CHUANG HARRY HAK-LAY | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 134 | 1997–2015 |
| Hsin Chu, TW | 6 | 2003–2012 |
| Hsinchu County, TW | 1 | 2004 |
| Taichung, TW | 1 | 1994 |