Inventor
Harold S. Crafts
Inventor
Colorado Springs, CO, US
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H03KPulse technique14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
G11CStatic stores11%
G06FElectric digital data processing7%
H10BElectronic memory devices7%
G01RMeasuring electric variables1%
H03MCoding1%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
7,257,779'Sea-of-cells array of transistors'20077,207,025'Sea-of-cells array of transistors'20076,977,399'Sea-of-cells array of transistors'20056,967,361'Sea-of-cells array of transistors'20056,801,969'Method and apparatus for data dependent, dual level output driver'20046,675,361'Method of constructing an integrated circuit comprising an embedded macro'20046,605,499'Method of forming sea-of-cells array of transistors'20036,557,066'Method and apparatus for data dependent, dual level output driver'20036,489,641'Sea-of-cells array of transistors'20026,294,937'Method and apparatus for self correcting parallel I/O circuitry'20016,269,466'Method of constructing an integrated circuit utilizing multiple layers of interconnect'20016,180,998'DRAM with built-in noise protection'20016,064,588'Embedded dram with noise-protected differential capacitor memory cells'20006,005,824'Inherently compensated clocking circuit for dynamic random access memory'19995,999,440'Embedded DRAM with noise-protecting substrate isolation well'19995,978,304'Hierarchical, adaptable-configuration dynamic random access memory'19995,973,952'Embedded DRAM with noise protecting shielding conductor'19995,920,110'Antifuse device for use on a field programmable interconnect chip'19995,907,511'Electrically selectable redundant components for an embedded DRAM'19995,901,095'Reprogrammable address selector for an embedded DRAM'19995,896,331'Reprogrammable addressing process for embedded DRAM'19995,869,900'Sea-of-cells array of transistors'19995,844,297'Antifuse device for use on a field programmable interconnect chip'19985,759,877'Semiconductor fuse structure'19985,671,397'Sea-of-cells array of transistors'19975,610,429'Differential analog transistors constructed from digital transistors'19975,541,548'Analog output driver for gate arrays'19965,536,968'Polysilicon fuse array structure for integrated circuits'19965,521,834'Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits'19965,497,027'Multi-chip module packaging system'19965,488,249'Differential analog transistors constructed from digital transistors'19965,481,207'High speed, low power input/output circuit for a multi-chip module'19965,444,401'Current limited output driver for a gate array circuit'19955,432,388'Repeatedly programmable logic array using dynamic access memory'19955,376,820'Semiconductor fuse structure'19945,341,046'Threshold controlled input circuit for an integrated circuit'19945,288,949'Connection system for integrated circuits which reduces cross-talk'19945,231,319'Voltage variable delay circuit'19935,185,652'Electrical connection between buses on a semiconductor integrated circuit'19935,140,180'High speed CMOS flip-flop employing clocked tristate inverters'19925,063,429'High density input/output cell arrangement for integrated circuits'19915,045,728'Trinary to binary level conversion circuit'19914,975,758'Gate isolated I.O cell architecture for diverse pad and drive configurations'19904,962,345'Current limiting output driver'19904,928,160'Gate isolated base cell structure with off-grid gate polysilicon pattern'19904,866,567'High frequency integrated circuit channel capacitor'19894,745,305'Common cell I/O interface circuit'19884,714,876'Circuit for initiating test modes'19874,647,798'Negative input voltage CMOS circuit'19874,048,673'CPU - I/O bus interface for a data processing system'19774,023,047'MOS pulse-edge detector circuit'1977Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1977Based in Saratoga, CA, US· patent location history
1987–1994Patents assigned to NCR CO (15)· patent assignee history
1987–1993Based in Fort Collins, CO, US· patent location history
1993–2007Based in Colorado Springs, CO, US· patent location history
1995–2004Patents assigned to HYUNDAI ELECTRONICS AMERICA (15)· patent assignee history
1995–1999Patents assigned to AT & T GLOBAL INF SOLUTION (12)· patent assignee history
1996–1999Patents assigned to SYMBIOS LOGIC INC (8)· patent assignee history
1999–2004Patents assigned to LSI LOGIC CORP (13)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HYUNDAI ELECTRONICS AMERICA | 15 | 1995–2004 |
| NCR CO | 15 | 1987–1994 |
| LSI LOGIC CORP | 13 | 1999–2004 |
| AT & T GLOBAL INF SOLUTION | 12 | 1995–1999 |
| SYMBIOS LOGIC INC | 8 | 1996–1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Colorado Springs, CO, US | 38 | 1993–2007 |
| Fort Collins, CO, US | 11 | 1987–1993 |
| Saratoga, California, US | 2 | 1977 |