Inventor

Paul Allen Ganfield

Inventor

Rochester, MN, US

Overview

42→

Patents

1997–2021

Patent span

Physics

Primary field (CPC G)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing39%

H04LTransmission of digital information, e.g. telegraphic communication19%

G11CStatic stores16%

G01RMeasuring electric variables11%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%

H03MCoding3%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

PatentTitleYear

10,969,822Reducing time of day latency variation in a multi processor system2021 10,693,595ACK clock compensation for high-speed serial communication interfaces2020 10,664,398Link-level cyclic redundancy check replay for non-blocking coherence flow2020 10,606,777Dropped command truncation for efficient queue utilization in multiprocessor data processing system2020 10,324,491Reducing time of day latency variation in a multi-processor system2019 10,128,985ACK clock compensation for high-speed serial communication interfaces2018 9,838,229Method for verifying the functionality of a digital circuit2017 9,565,014'Initializing a descrambler'2017 9,548,857'Initializing a descrambler'2017 9,515,813'Initializing a descrambler'2016 9,495,312'Determining command rate based on dropped commands'2016 9,497,020'Initializing a descrambler'2016 9,495,314'Determining command rate based on dropped commands'2016 8,510,512'Memory coherence directory supporting remotely sourced requests of nodal scope'2013 8,504,779'Memory coherence directory supporting remotely sourced requests of nodal scope'2013 8,219,745'Memory controller to utilize DRAM write buffers'2012 7,925,823'Reuse of functional data buffers for pattern buffers in XDR DRAM'2011 7,761,682'Memory controller operating in a system with a variable system clock'2010 7,752,379'Managing write-to-read turnarounds in an early read after write memory system'2010 7,716,430'Separate handling of read and write of read-modify-write'2010 7,676,639'Separate handling of read and write of read-modify-write'2010 7,617,332'Method and apparatus for implementing packet command instructions for network processing'2009 7,487,318'Managing write-to-read turnarounds in an early read after write memory system'2009 7,467,277'Memory controller operating in a system with a variable system clock'2008 7,380,052'Reuse of functional data buffers for pattern buffers in XDR DRAM'2008 7,363,442'Separate handling of read and write of read-modify-write'2008 7,321,950'Method and apparatus for managing write-to-read turnarounds in an early read after write memory system'2008 7,287,103'Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes'2007 7,272,699'Flexible sub-column to sub-row mapping for sub-page activation in XDRâ„¢ DRAMs'2007 7,266,650'Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts'2007 7,248,595'Method, apparatus, and computer program product for implementing packet ordering'2007 7,240,166'Method and apparatus for implementing packet work area accesses and buffer sharing'2007 7,225,097'Methods and apparatus for memory calibration'2007 7,089,387'Methods and apparatus for maintaining coherency in a multi-processor system'2006 6,909,315'Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)'2005 6,260,164'SRAM that can be clocked on either clock phase'2001 6,195,775'Boundary scan latch configuration for generalized scan designs'2001 6,178,534'System and method for using LBIST to find critical paths in functional logic'2001 6,158,032'Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof'2000 5,835,502'Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme'1998 5,815,694'Apparatus and method to change a processor clock frequency'1998 5,663,966'System and method for minimizing simultaneous switching during scan-based testing'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2021Patents assigned to IBM (42)· patent assignee history

1997–2021Based in Rochester, MN, US· patent location history

2013Patents assigned to GANFIELD PAUL A (2)· patent assignee history

2013Patents assigned to GUTHRIE GUY L (2)· patent assignee history

2013Patents assigned to KROLAK DAVID J (2)· patent assignee history

2013Patents assigned to SIEGEL MICHAEL S (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	42	1997–2021
GANFIELD PAUL Aself	2	2013
GUTHRIE GUY L	2	2013
KROLAK DAVID J	2	2013
SIEGEL MICHAEL S	2	2013

Locations

Location	Patents	Span
Rochester, Minnesota, US	42	1997–2021