Inventor
Cécile Aulnette
Inventor
Grenoble, FR
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H10DInorganic electric semiconductor devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
C30BSingle-crystal growth6%
H01LSemiconductor devices5%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
10,361,326Advanced CPV solar cell assembly process20199,954,139Multiple transfer assembly process20189,177,961'Wafer with intrinsic semiconductor layer'20159,018,678'Method for forming a Ge on III/V-on-insulator structure'20158,367,521'Manufacture of thin silicon-on-insulator (SOI) structures'20138,324,075'Methods for recycling substrates and fabricating laminated wafers'20128,183,128'Method of reducing roughness of a thick insulating layer'20127,602,046'Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof'20097,572,714'Film taking-off method'20097,544,976'Semiconductor heterostructure'20097,459,374'Method of manufacturing a semiconductor heterostructure'20087,446,019'Method of reducing roughness of a thick insulating layer'20087,407,867'Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate'20087,378,729'Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom'20087,375,008'Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof'20087,256,075'Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer'20077,232,743'Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same'20077,232,488'Method of fabrication of a substrate for an epitaxial growth'20077,115,481'Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate'20067,078,353'Indirect bonding with disappearance of bonding layer'20067,033,905'Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means'20067,018,910'Transfer of a thin layer from a wafer comprising a buffer layer'20067,008,857'Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom'20066,995,427'Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same'20066,991,995'Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer'20066,991,956'Methods for transferring a thin layer from a wafer having a buffer layer'20066,955,971'Semiconductor structure and methods for fabricating same'20056,908,774'Method and apparatus for adjusting the thickness of a thin layer of semiconductor material'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2019Patents assigned to SOITEC SILICON ON INSULATOR (26)· patent assignee history
2005–2012Based in Grenoble, FR· patent location history
2006–2008Patents assigned to COMMISSARIAT ENERGIE ATOMIQUE (3)· patent assignee history
2012–2015Patents assigned to AULNETTE CECILE (4)· patent assignee history
2012–2015Patents assigned to DAVAL NICOLAS (4)· patent assignee history
2012–2015Based in Guilderland, NY, US· patent location history
2015Patents assigned to NGUYEN BICH-YEN (2)· patent assignee history
2015Based in Crolles, FR· patent location history
2018–2019Based in Lumbin, FR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SOITEC SILICON ON INSULATOR | 26 | 2005–2019 |
| AULNETTE CECILEself | 4 | 2012–2015 |
| DAVAL NICOLAS | 4 | 2012–2015 |
| COMMISSARIAT ENERGIE ATOMIQUE | 3 | 2006–2008 |
| NGUYEN BICH-YEN | 2 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Grenoble, FR | 22 | 2005–2012 |
| Guilderland, New York, US | 3 | 2012–2015 |
| Lumbin, FR | 2 | 2018–2019 |
| Crolles, FR | 1 | 2015 |