Inventor
Ninh D. Ngo
Inventor
San Jose, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique38%
G06FElectric digital data processing21%
G11CStatic stores15%
H03MCoding15%
G01RMeasuring electric variables4%
H04LTransmission of digital information, e.g. telegraphic communication4%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
PatentTitleYear
9,438,418'Systems and methods for generating a key difficult to clone'20169,172,505'Methods and apparatus for frame detection'20158,797,061'Partial reconfiguration circuitry'20148,694,864'Parallel processing error detection and location circuitry for configuration random-access memory'20148,661,321'Parallel processing error detection and location circuitry for configuration random-access memory'20148,281,215'Parallel processing error detection and location circuitry for configuration random-access memory'20128,130,574'Error detection on programmable logic resources'20128,032,817'Error detection and location circuitry for configuration random-access memory'20117,907,460'Error detection on programmable logic resources'20117,844,886'Parallel processing error detection and location circuitry for configuration random-access memory'20107,702,978'Soft error location and sensitivity detection for programmable devices'20107,634,713'Error detection and location circuitry for configuration random-access memory'20097,602,255'Loop circuits that reduce bandwidth variations'20097,577,055'Error detection on programmable logic resources'20097,310,757'Error detection on programmable logic resources'20077,215,140'Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method'20077,205,791'Bypass-able carry chain in a programmable logic device'20077,178,117'Apparatus and method for RTL based full chip modeling of a programmable logic device'20077,112,992'Configuration shift register'20067,061,268'Initializing a carry chain in a programmable logic device'20066,842,039'Configuration shift register'20056,366,121'Programmable logic array integrated circuit architectures'20025,999,016'Architectures for programmable logic devices'19995,963,049'Programmable logic array integrated circuit architectures'19995,909,126'Programmable logic array integrated circuit devices with interleaved logic array blocks'19995,821,787'Power-on reset circuit with well-defined reassertion voltage'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2016Patents assigned to ALTERA CORP (26)· patent assignee history
1998–2012Based in San Jose, CA, US· patent location history
2009–2016Based in Palo Alto, CA, US· patent location history
2012–2016Patents assigned to NGO NINH D (7)· patent assignee history
2012Patents assigned to LEE ANDY L (1)· patent assignee history
2014Patents assigned to MARGABANDU BALAJI (1)· patent assignee history
2014Patents assigned to MAUNG LEO MIN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 26 | 1998–2016 |
| NGO NINH Dself | 7 | 2012–2016 |
| LEE ANDY L | 1 | 2012 |
| MARGABANDU BALAJI | 1 | 2014 |
| MAUNG LEO MIN | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 15 | 1998–2012 |
| Palo Alto, California, US | 11 | 2009–2016 |