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Inventor

Sailesh Chittipeddi

Inventor
Allentown, PA, US

Overview

64→
Patents
1991–2013
Patent span
Electricity
Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10BElectronic memory devices7%
C23CCoating metallic material5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G01RMeasuring electric variables2%
G06FElectric digital data processing1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
8,507,317'Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore'20138,030,199'Transistor fabrication method'20117,952,206'Solder bump structure for flip chip semiconductor devices and method of manufacture therefore'20117,727,894'Formation of an integrated circuit structure with reduced dishing in metallization levels'20107,563,669'Integrated circuit with a trench capacitor structure and method of manufacture'20096,838,769'Dual damascene bond pad structure for lowering stress and allowing circuitry under pads'20056,790,757'Wire bonding method for copper interconnects in semiconductor devices'20046,773,994'CMOS vertical replacement gate (VRG) transistors'20046,762,087'Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor'20046,706,603'Method of forming a semiconductor device'20046,628,001'Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same'20036,615,195'Method and system for evaluating technology transfer value'20036,556,409'Integrated circuit including ESD circuits for a multi-chip module and a method therefor'20036,552,381'Trench capacitors in SOI substrates'20036,538,283'Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer'20036,503,793'Method for concurrently forming an ESD protection device and a shallow trench isolation region'20036,500,729'Method for reducing dishing related issues during the formation of shallow trench isolation structures'20026,498,080'Transistor fabrication method'20026,482,694'Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers'20026,472,304'Wire bonding to copper'20026,455,418'Barrier for copper metallization'20026,445,043'Isolated regions in an integrated circuit'20026,426,263'Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain'20026,417,087'Process for forming a dual damascene bond pad structure over active circuitry'20026,387,772'Method for forming trench capacitors in SOI substrates'20026,384,452'Electrostatic discharge protection device with monolithically formed resistor-capacitor portion'20026,365,469'Method for forming dual-polysilicon structures using a built-in stop layer'20026,365,327'Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit'20026,358,785'Method for forming shallow trench isolation structures'20026,348,393'Capacitor in an integrated circuit and a method of manufacturing an integrated circuit'20026,323,126'Tungsten formation process'20016,319,837'Technique for reducing dishing in Cu-based interconnects'20016,313,025'Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit'20016,294,807'Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers'20016,288,449'Barrier for copper metallization'20016,265,890'In-line non-contact depletion capacitance measurement method and apparatus'20016,246,325'Distributed communications system for reducing equipment down-time'20016,230,293'Method for quality and reliability assurance testing of integrated circuits using differential Iddq screening in lieu of burn-in'20016,207,547'Bond pad design for integrated circuits'20016,191,017'Method of forming a multi-layered dual-polysilicon structure'20016,187,658'Bond pad for a flip chip package, and method of forming the same'20016,136,159'Method for depositing metal'20006,136,620'Method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein'20006,087,732'Bond pad for a flip-chip package'20006,080,625'Method for making dual-polysilicon structures in integrated circuits'20006,078,035'Integrated circuit processing utilizing microwave radiation'20006,017,787'Integrated circuit with twin tub'20005,986,343'Bond pad design for integrated circuits'19995,972,179'Silicon IC contacts using composite TiN barrier layer'19995,965,903'Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein'19995,935,396'Method for depositing metal'19995,918,116'Process for forming gate oxides possessing different thicknesses on a semiconductor substrate'19995,891,784'Transistor fabrication method'19995,807,760'Method of despositing an aluminum-rich layer'19985,798,300'Method for forming conductors in integrated circuits'19985,773,867'Programmable hex-ROM with isolation transistor structure'19985,763,314'Process for forming isolation regions in an integrated circuit'19985,751,065'Integrated circuit with active devices under bond pads'19985,589,416'Process for forming integrated capacitors'19965,573,965'Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology'19965,439,847'Integrated circuit fabrication with a raised feature as mask'19955,268,329'Method of fabricating an integrated circuit interconnection'19935,147,820'Silicide formation on polysilicon'19925,045,486'Transistor fabrication method'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–1993Patents assigned to AT & T BELL LAB (3)· patent assignee history
1991–2011Based in Whitehall, PA, US· patent location history
1996–2003Patents assigned to LUCENT TECHNOLOGIES INC (27)· patent assignee history
1996–2000Based in Austin, TX, US· patent location history
1998–2002Based in Lehigh County, PA, US· patent location history
1998–1999Based in Emmaus, PA, US· patent location history
1999–2013Based in Allentown, PA, US· patent location history
2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (16)· patent assignee history
2002–2011Patents assigned to AGERE SYSTEMS INC (15)· patent assignee history
2002Patents assigned to AGERE SYSTEMS (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LUCENT TECHNOLOGIES INC271996–2003
AGERE SYST GUARDIAN CORP162001–2002
AGERE SYSTEMS INC152002–2011
AT & T BELL LAB31991–1993
AGERE SYSTEMS12002
Locations
LocationPatentsSpan
Allentown, Pennsylvania, US431999–2013
Whitehall, Pennsylvania, US101991–2011
Austin, Texas, US51996–2000
Lehigh County, Pennsylvania, US31998–2002
Emmaus, Pennsylvania, US21998–1999