Inventor
Charles Walter Pearce
Inventor
Emmaus, PA, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
H10BElectronic memory devices5%
C30BSingle-crystal growth3%
A47LDomestic washing or cleaning2%
B08BCleaning in general2%
B24BMachines, devices, or processes for grinding or polishing2%
B41JTypewriters2%
PatentTitleYear
8,294,210'High voltage channel diode'20128,288,820'High voltage power integrated circuit'20127,927,940'Method of manufacturing a laterally diffused metal oxide semiconductor device'20117,927,939'Method of manufacturing a laterally diffused metal oxide semiconductor device'20117,638,380'Method for manufacturing a laterally diffused metal oxide semiconductor device'20096,855,991'Semiconductor device having a doped lattice matching layer and a method of manufacture therefor'20056,762,457'LDMOS device having a tapered oxide'20046,737,339'Semiconductor device having a doped lattice matching layer and a method of manufacture therefor'20046,552,381'Trench capacitors in SOI substrates'20036,537,135'Curvilinear chemical mechanical planarization device and method'20036,506,641'Use of selective oxidation to improve LDMOS power transistors'20036,503,841'Oxide etch'20036,482,694'Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers'20026,472,279'Method of manufacturing a channel stop implant in a semiconductor device'20026,387,772'Method for forming trench capacitors in SOI substrates'20026,361,614'Dark spin rinse/dry'20026,358,865'Oxidation of silicon using fluorine implant'20026,294,807'Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers'20016,245,692'Method to selectively heat semiconductor wafers'20015,930,650'Method of etching silicon materials'19995,711,891'Wafer processing using thermal nitride etch mask'19985,488,749'Sink and disposal cleaning tool'19965,336,371'Semiconductor wafer cleaning and rinsing techniques using re-ionized water and tank overflow'19945,224,311'Trailer anchor apparatus'19934,347,431'Diffusion furnace'19824,216,489'MOS Dynamic memory in a diffusion current limited semiconductor structure'19804,134,785'Real-time analysis and control of melt-chemistry in crystal growing operations'19794,131,487'Gettering semiconductor wafers with a high energy laser beam'1978Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1978–1980Patents assigned to WESTERN ELECTRIC CO (3)· patent assignee history
1978–2012Based in Emmaus, PA, US· patent location history
1979Based in Allentown, PA, US· patent location history
1980–1982Patents assigned to BELL TELEPHONE LABOR INC (2)· patent assignee history
1993Based in Pitsea, GB· patent location history
1996Based in Annapolis, MD, US· patent location history
2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (5)· patent assignee history
2002–2011Patents assigned to AGERE SYSTEMS INC (12)· patent assignee history
2012Patents assigned to KOCON CHRISTOPHER BOGUSLAW (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AGERE SYSTEMS INC | 12 | 2002–2011 |
| AGERE SYST GUARDIAN CORP | 5 | 2001–2002 |
| WESTERN ELECTRIC CO | 3 | 1978–1980 |
| BELL TELEPHONE LABOR INC | 2 | 1980–1982 |
| KOCON CHRISTOPHER BOGUSLAW | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Emmaus, Pennsylvania, US | 25 | 1978–2012 |
| Annapolis, Maryland, US | 1 | 1996 |
| Pitsea, GB | 1 | 1993 |
| Allentown, Pennsylvania, US | 1 | 1979 |