Inventor

Norman J. Rasmussen

Inventor
Hillsboro, OR, US

Overview

19→
Patents
1995–2003
Patent span
Physics
Primary field (CPC G)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
6,594,717'Apparatus and method for dedicated interconnection over a shared external bus'20036,502,146'Apparatus and method for dedicated interconnection over a shared external bus'20026,434,692'High-throughput interface between a system memory controller and a peripheral device'20026,317,803'High-throughput interconnect having pipelined and non-pipelined bus transaction modes'20016,266,719'High-throughput interface between a system memory controller and a peripheral device'20016,167,468'High-throughput interface between a system memory controller and a peripheral device'20006,112,016'Method and apparatus for sharing a signal line between agents'20006,047,355'Symmetric multiprocessing system with unified environment and distributed system functions'20006,006,291'High-throughput interface between a system memory controller and a peripheral device'19995,948,094'Method and apparatus for executing multiple transactions within a single arbitration cycle'19995,887,194'Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked'19995,832,241'Data consistency across a bus transactions that impose ordering constraints'19985,822,767'Method and apparartus for sharing a signal line between agents'19985,809,340'Adaptively generating timing signals for access to various memory devices based on stored profiles'19985,768,548'Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data'19985,740,376'Signaling protocol for a peripheral component interconnect'19985,651,137'Scalable cache attributes for an input/output bus'19975,522,069'Symmetric multiprocessing system with unified environment and distributed system functions'19965,467,295'Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2003Patents assigned to INTEL CORP (18)· patent assignee history
1995–2003Based in Hillsboro, OR, US· patent location history
1996Patents assigned to ZENITH DATA SYSTEMS CORP (1)· patent assignee history
1998Patents assigned to PACKARD BELL NEC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP181995–2003
PACKARD BELL NEC11998
ZENITH DATA SYSTEMS CORP11996
Locations
LocationPatentsSpan
Hillsboro, OR, US191995–2003