Inventor
Ankireddy NALAMALPU
Inventor
US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H01LSemiconductor devices14%
H03KPulse technique12%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
H04LTransmission of digital information, e.g. telegraphic communication6%
G01RMeasuring electric variables2%
H05KPrinted circuits2%
G05BControl or regulating systems in general2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
PatentTitleYear
12,599,021Homogenous die stacking with increased element density202612,593,675Reticle stitching to achieve high-capacity integrated circuit202612,525,980Systems and methods for dynamic power and thermal management for programmable logic devices202612,487,658Workload-dependent integrated circuit operation based on power headroom202512,481,345Techniques for power management in compute circuits202512,437,135Dynamic loadlines for programmable fabric devices202512,431,899Self-gating flops for dynamic power reduction202512,429,900Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop202512,422,477Segmented row repair for programmable logic devices202512,379,698Systems and methods to reduce voltage guardband202512,353,238Flexible instruction set architecture supporting varying frequencies202512,355,359Switch based on load current202512,347,783Interconnect architecture with silicon interposer and EMIB202512,341,511Power management using voltage islands on programmable logic devices202512,334,449Selective use of different advanced interface bus with electronic chips202512,294,368Three-dimensional stacked programmable logic fabric and processor design architecture202512,273,107Dynamically scalable timing and power models for programmable logic devices202512,266,625Innovative interconnect design for package architecture to improve latency202512,237,831Network-on-chip (NOC) with flexible data width202512,216,150On-die aging measurements for dynamic timing modeling202512,206,410Programmable logic device with fine-grained disaggregation202512,153,866Modular periphery tile for integrated circuit device202412,038,858Processor package with universal optical input/output202412,026,008Techniques for clock signal transmission in integrated circuits and interposers202412,007,929Low-latency optical connection for CXL for a server CPU202411,983,135Electrical and optical interfaces at different heights along an edge of a package to increase bandwidth along the edge202411,929,339Innovative interconnect design for package architecture to improve latency202411,915,996Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling202411,901,299Interconnect architecture with silicon interposer and EMIB202411,789,883Inter-die communication of programmable logic devices202311,714,941Modular periphery tile for integrated circuit device202311,700,002Network-on-chip (NOC) with flexible data width202311,669,472Frequency translation circuitry for an interconnection in an active interposer of a semiconductor package202311,658,144Innovative interconnect design for package architecture to improve latency202311,621,713High-speed core interconnect for multi-die programmable logic devices202311,609,262On-die aging measurements for dynamic timing modeling202311,610,856Connectivity between integrated circuit dice in a multi-chip package202311,595,045Programmable logic device with fine-grained disaggregation202311,557,541Interconnect architecture with silicon interposer and EMIB202311,538,753Electronic chip with under-side power block202211,528,029Apparatus to synchronize clocks of configurable integrated circuit dies through an interconnect bridge202211,500,412Techniques for clock signal transmission in integrated circuits and interposers202211,368,158Methods for handling integrated circuit dies with defects202211,342,238Rotatable architecture for multi-chip package (MCP)202211,342,918Network-on-chip (NOC) with flexible data width202211,216,397Translation circuitry for an interconnection in an active interposer of a semiconductor package2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to INTEL CORP (45)· patent assignee history
2022–2026Based in US· patent location history
2024–2026Patents assigned to ALTERA CORP (16)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 45 | 2022–2026 |
| ALTERA CORP | 16 | 2024–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 46 | 2022–2026 |