Inventor
THOMAS J. GIOVANNINI
Inventor
US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing47%
G11CStatic stores42%
H04LTransmission of digital information, e.g. telegraphic communication7%
H01LSemiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
12,463,849Burst-tolerant decision feedback equalization202512,436,907Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules202512,386,763Protocol including selective output by memory of a timing reference signal202512,314,162Circuits and methods for self-adaptive decision-feedback equalization in a memory system202512,298,842Memory module register access202512,298,926High-performance, high-capacity memory systems and modules202512,210,467Memory modules and systems with variable-width data ranks and configurable data-rank timing202512,136,452Method and apparatus for calibrating write timing in a memory system202412,062,413Signal receiver with skew-tolerant strobe gating202411,953,981Memory module register access202411,949,539Burst-tolerant decision feedback equalization202411,816,047Protocol including a command-specified timing reference signal202311,815,940Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules202311,809,345Data-buffer component with variable-width data ranks and configurable data-rank timing202311,763,865Signal receiver with skew-tolerant strobe gating202311,755,508High-performance, high-capacity memory systems and modules202311,682,448Method and apparatus for calibrating write timing in a memory system202311,573,849Memory module register access202311,404,103Method and apparatus for calibrating write timing in a memory system202211,341,070Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules202211,275,702Memory module and registered clock driver with configurable data-rank timing202211,211,114Memories and memory components with interconnected and redundant data interfaces202111,184,197Burst-tolerant decision feedback equalization2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to RAMBUS INC (23)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 23 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 23 | 2021–2025 |