Inventor
JOHANN ALSMEIER
Inventor
US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices32%
H01LSemiconductor devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10DInorganic electric semiconductor devices11%
G11CStatic stores10%
H10NElectric solid-state devices not otherwise provided for2%
G06FElectric digital data processing1%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
PatentTitleYear
12,532,463Three-dimensional memory device with separated source lines and method of making the same202612,456,499Three-dimensional memory device including laterally separated source lines and method of making the same202512,349,353Three-dimensional nor array and method of making the same202512,322,710Three-dimensional memory device with finned support pillar structures and method of forming the same202512,279,445Field effect transistors with gate fins and method of making the same202512,243,865Bonded semiconductor die assembly containing through-stack via structures and methods for making the same202512,148,710Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same202412,096,632Three-dimensional memory device with multiple types of support pillar structures and method of forming the same202412,087,371Preventing erase disturb in NAND202412,029,036Three-dimensional memory device with multiple types of support pillar structures and method of forming the same202411,968,839Memory device using a multilayer ferroelectric stack and method of forming the same202411,903,218Bonded memory devices and methods of making the same202411,871,580Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same202411,856,765Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same202311,805,649Three-dimensional memory device with wiggled drain-select-level isolation structure and methods of manufacturing the same202311,587,920Bonded semiconductor die assembly containing through-stack via structures and methods for making the same202311,552,094Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same202311,538,817Bonded memory devices and methods of making the same202211,532,570Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same202211,489,043Three-dimensional memory device employing thinned insulating layers and methods for forming the same202211,481,154Non-volatile memory with memory array between circuits202211,469,251Memory device using a multilayer ferroelectric stack and method of forming the same2022RE049165On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same202211,398,496Three-dimensional memory device employing thinned insulating layers and methods for forming the same202211,387,142Semiconductor device containing bit lines separated by air gaps and methods for forming the same202211,380,707Three-dimensional memory device including backside trench support structures and methods of forming the same202211,296,101Three-dimensional memory device including an inter-tier etch stop layer and method of making the same202211,251,199Three-dimensional NOR array including active region pillars and method of making the same202211,222,881Three-dimensional memory device with logic signal routing through a memory die and methods of making the same202211,195,857Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer202111,164,890Cross-point array of ferroelectric field effect transistors and method of making the same202111,139,272Bonded assembly containing oxidation barriers and/or adhesion enhancers and methods of forming the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to SANDISK TECHNOLOGIES LLC (32)· patent assignee history
2021–2026Based in US· patent location history
2025–2026Patents assigned to SANDISK TECHNOLOGIES INC (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 32 | 2021–2026 |
| SANDISK TECHNOLOGIES INC | 6 | 2025–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 32 | 2021–2026 |