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Inventor

Madhu Athreya

Inventor
Saratoga, CA, US

Overview

22→
Patents
2009–2019
Patent span
Physics
Primary field (CPC G)

Patents· 22 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing61%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
G06TImage data processing or generation, in general6%
H04NPictorial communication, e.g. television6%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
PatentTitleYear
10,200,662Color corrected images for projectors20199,800,781'Method, apparatus, system, and computer readable medium for image processing software module configuration'20179,600,433'System, apparatus and method for integrating non-peripheral component interconnect (PCI) resources into a personal computer system'20179,547,618'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)'20179,158,363'Power management for a system on a chip (SoC)'20158,850,247'Power management for a system on a chip (SoC)'20148,751,722'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)'20148,745,303'Integrating non-peripheral component interconnect (PCI) resources into a computer system'20148,510,580'Power management for a system on a chip (SoC)'20138,471,865'System, method and apparatus for an edge-preserving smooth filter for low power architecture'20138,463,975'Integrating non-peripheral component interconnect (PCI) resources into a personal computer system'20138,433,841'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)'20138,286,014'Power management for a system on a chip (SoC)'20128,209,456'Integrating non-peripheral component interconnect (PCI) resources into a personal computer system'20128,205,029'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)'20128,037,230'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)'20118,010,731'Integrating non-peripheral component interconnect (PCI) resource into a personal computer system'20117,861,027'Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)'20107,844,854'Opportunistic transmission of computing system state information within a link based computing system'20107,813,288'Transaction detection in link based computing system'20107,783,819'Integrating non-peripheral component interconnect (PCI) resources into a personal computer system'20107,496,801'Method, apparatus and system for facilitating debug for link interconnects'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2017Patents assigned to INTEL CORP (21)· patent assignee history
2009–2017Based in Saratoga, CA, US· patent location history
2012–2013Patents assigned to ATHREYA MADHU (7)· patent assignee history
2012–2013Patents assigned to HAN WOOJONG (6)· patent assignee history
2012–2013Patents assigned to MANDHANI ARVIND (6)· patent assignee history
2012–2013Patents assigned to SHOEMAKER KEN (6)· patent assignee history
2019Based in Palo Alto, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP212009–2017
ATHREYA MADHUself72012–2013
HAN WOOJONG62012–2013
MANDHANI ARVIND62012–2013
SHOEMAKER KEN62012–2013
Locations
LocationPatentsSpan
Saratoga, California, US212009–2017
Palo Alto, California, US12019