Inventor
Russ W. Herrell
Inventor
Fort Collins, CO, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing77%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
G11CStatic stores4%
H04LTransmission of digital information, e.g. telegraphic communication4%
A61BDiagnosis2%
G01RMeasuring electric variables2%
G06TImage data processing or generation, in general2%
H05KPrinted circuits2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
11,126,372External memory controller202110,922,178Masterless raid for byte-addressable non-volatile memory202110,817,361Controlling error propagation due to fault in computing node of a distributed computing system202010,664,410Transmitting contents of an operation field to a media controller202010,474,380External memory controller201910,452,567Non-volatile memory to store resettable data201910,452,498Fault tolerance for persistent main memory201910,318,767Multi-tier security framework201910,289,467Error coordination message for a blade device having a logical processor in another system firmware domain201910,241,715Rendering data invalid in a memory array201910,235,078Meta-data block within a non-volatile memory device20199,990,244Controlling error propagation due to fault in computing node of a distributed computing system20189,927,988'Data move engine to move a block of data'20189,921,747'Unifying memory controller'20189,830,283Multi-mode agent20179,781,015'Making memory of compute and expansion devices available for use by an operating system'20179,747,116'Identifying memory of a blade device for use by an operating system of a partition including the blade device'20179,277,680'Blade computer system'20169,207,990'Method and system for migrating critical resources within computer systems'20158,812,915'Determining whether a right to use memory modules in a reliability mode has been acquired'20148,782,779'System and method for achieving protected region within computer system'20148,656,236'Remote boundary scanning'20148,612,973'Method and system for handling interrupts within computer system during hardware resource migration'20138,505,020'Computer workload migration using processor pooling'20138,473,673'Memory controller based (DE)compression'20138,327,168'System and method for throttling memory power consumption'20128,112,611'Allocating resources to partitions in a partitionable computer'20128,006,103'TPM device for multi-processor systems'20117,814,301'Clock architecture for multi-processor systems'20107,694,064'Multiple cell computer systems and methods'20107,650,275'Virtualization of a parition based on addresses of an I/O adapter within an external emulation unit'20107,606,995'Allocating resources to partitions in a partitionable computer'20097,600,082'Virtualization logic'20097,480,755'Trap mode register'20097,472,292'System and method for throttling memory power consumption based on status of cover switch of a computer system'20087,373,457'Cache coherence protocol for a multiple bus multiprocessor system'20087,363,484'Apparatus and method for selectively mapping proper boot image to processors of heterogeneous computer systems'20086,868,481'Cache coherence protocol for a multiple bus multiprocessor system'20056,574,710'Computer cache system with deferred invalidation'20035,896,141'System and method for virtual device access in a computer system'19995,416,893'Method for displaying edging or decaling of an object in a graphics display'19955,347,634'System and method for directly executing user DMA instruction from user controlled process by employing processor privileged work buffer pointers'19945,325,493'System for distributing command/data packets tagged by their unit identifier for parallel processing by a ready processing unit and recombination'19945,301,287'User scheduled direct memory access using virtual addresses'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1999Patents assigned to HEWLETT PACKARD CO (5)· patent assignee history
1994–2021Based in Fort Collins, CO, US· patent location history
2003–2019Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (26)· patent assignee history
2012–2016Patents assigned to HERRELL RUSS W (7)· patent assignee history
2012–2015Patents assigned to MORRISON JOHN A (4)· patent assignee history
2016–2021Patents assigned to HEWLETT PACKARD ENTPR DEV LP (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEWLETT PACKARD DEVELOPMENT CO | 26 | 2003–2019 |
| HEWLETT PACKARD ENTPR DEV LP | 18 | 2016–2021 |
| HERRELL RUSS Wself | 7 | 2012–2016 |
| HEWLETT PACKARD CO | 5 | 1994–1999 |
| MORRISON JOHN A | 4 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fort Collins, CO, US | 44 | 1994–2021 |