Inventor
KARTHIK SARPATWARI
Inventor
US
Overview
Patents· 69 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores39%
H10BElectronic memory devices22%
H01LSemiconductor devices16%
H10DInorganic electric semiconductor devices13%
G06FElectric digital data processing3%
H10NElectric solid-state devices not otherwise provided for3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
G06NComputing arrangements based on specific computational models1%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
PatentTitleYear
12,537,054Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells202612,484,208Memory device having tiers of 2-transistor memory cells and charge storage structure having multiple portions202512,432,898Memory device having tiers of 2-transistor memory cells202512,361,977Memory device having shared read/write data line for 2-transistor vertical memory cell202512,349,335Memory device having 2-transistor vertical memory cell and shared channel region202512,266,660Memory device having 2-transistor memory cell and access line plate202512,219,750Memory device having 2-transistor vertical memory cell and separate read and write gates202512,176,029Drift aware read operations202412,106,803Multi-step pre-read for write operations in memory devices202412,101,946Integrated assemblies comprising hydrogen diffused within two or more different semiconductor materials, and methods of forming integrated assemblies202412,080,331Memory device having 2-transistor vertical memory cell and shield structures202412,080,359Identify the programming mode of memory cells during reading of the memory cells202412,069,853Memory device having shared access line for 2-transistor vertical memory cell202412,014,784Evaluation of background leakage to select write voltage in memory devices202411,985,806Vertical 2-transistor memory cell202411,950,402Memory device having 2-transistor vertical memory cell and shield structures202411,950,426Memory device having 2-transistor vertical memory cell and wrapped data line structure202411,942,139Performing refresh operations on memory cells202411,942,136Memory device having shared read/write access line for 2-transistor vertical memory cell202411,923,007Dirty write on power off202411,894,078Accessing a multi-level memory cell202411,875,867Weighted wear leveling for improving uniformity202411,871,589Memory device having 2-transistor memory cell and access line plate202411,862,226Systems and methods for pre-read scan of memory devices202411,832,454Integrated assemblies comprising hydrogen diffused within two or more different semiconductor materials, and methods of forming integrated assemblies202311,791,391Inverters, and related memory devices and electronic systems202311,783,902Multi-state programming of memory cells202311,782,830Cache memory with randomized eviction202311,776,907Memory device having 2-transistor vertical memory cell and a common plate202311,775,431Cache memory with randomized eviction202311,778,806Memory device having 2-transistor vertical memory cell and separate read and write gates202311,735,258Increase of a sense current in memory202311,727,983Single word line gain cell with complementary read write channel202311,728,005Bipolar read retry202311,710,528Data-based polarity write operations202311,694,747Self-selecting memory cells configured to store more than one bit per memory cell202311,688,450Memory device having 2-transistor vertical memory cell and shield structures202311,664,074Programming intermediate state to store data in self-selecting memory cells202311,664,073Adaptively programming memory cells in different modes to optimize performance202311,665,880Memory device having 2-transistor vertical memory cell and a common plate202311,653,489Memory device having 2-transistor vertical memory cell and shield structures202311,631,453Vertical 3D single word line gain cell with shared read/write bit line202311,616,073Memory device having 2-transistor vertical memory cell and wrapped data line structure202311,615,854Identify the programming mode of memory cells during reading of the memory cells202311,616,098Three-dimensional memory arrays, and methods of forming the same202311,568,952Adjustable programming pulses for a multi-level cell202311,545,194Dynamic read voltage techniques202311,545,216Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device202311,538,513Memory element for weight update in a neural network202211,532,347Performing refresh operations of non-volatile memory to mitigate read disturb202211,527,287Drift aware read operations202211,514,983Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells202211,508,437Restoring memory cell threshold voltages202211,475,970Bipolar read retry202211,476,252Memory device having 2-transistor vertical memory cell and shared channel region202211,417,381Memory device having shared read/write access line for 2-transistor vertical memory cell202211,404,130Evaluation of background leakage to select write voltage in memory devices202211,367,484Multi-step pre-read for write operations in memory devices202211,367,483Techniques for applying multiple voltage pulses to select a memory cell202211,355,209Accessing a multi-level memory cell202211,355,554Sense lines in three-dimensional memory arrays, and methods of forming the same202211,335,684Memory device having 2-transistor memory cell and access line plate202211,295,822Multi-state programming of memory cells202211,296,094Memory device having shared access line for 2-transistor vertical memory cell202211,295,811Increase of a sense current in memory202211,222,690Vertical 3D single word line gain cell with shared read/write bit line202211,195,998Memory structures having improved write endurance202111,139,016Read refresh operation202111,139,034Data-based polarity write operations2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (68)· patent assignee history
2021Patents assigned to INTEL CORP (1)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 68 | 2021–2026 |
| INTEL CORP | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 69 | 2021–2026 |