LexDanaLexDanabeta
Inventor

Gregg A. Bouchard

Inventor
Georgetown, TX, US

Overview

66→
Patents
1994–2021
Patent span
Physics
Primary field (CPC G)

Patents· 66 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing30%
H04LTransmission of digital information, e.g. telegraphic communication20%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
G11CStatic stores12%
G06NComputing arrangements based on specific computational models11%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications11%
F02BInternal-combustion piston engines1%
H01LSemiconductor devices1%
H04WWireless communication networks1%
PatentTitleYear
11,132,049Methods and apparatus for adaptive power profiling in a baseband processing system202111,061,724Programmable hardware scheduler for digital processing systems202111,010,318Method and apparatus for efficient and flexible direct memory access202110,740,256Re-ordering buffer for a digital multi-processor system with configurable, scalable, distributed job manager202010,713,089Method and apparatus for load balancing of jobs scheduled for processing202010,635,497Method and apparatus for job pre-scheduling by distributed job manager in a digital multi-processor system202010,496,329Methods and apparatus for a unified baseband architecture201910,466,964Engine architecture for processing finite automata201910,423,215Methods and apparatus for adaptive power profiling in a baseband processing system201910,277,510System and method for storing lookup request rules in multiple memories20199,866,540'System and method for rule matching in a processor'20189,785,403'Engine architecture for processing finite automata'20179,729,527'Lookup front end packet input processor'20179,652,505'Content search pattern matching using deterministic finite automata (DFA) graphs'20179,614,762'Work migration in a processor'20179,596,222'Method and apparatus encoding a rule for a lookup request in a processor'20179,569,366'System and method to provide non-coherent access to a coherent memory system'20179,531,723'Phased bucket pre-fetch in a network processor'20169,531,690'Method and apparatus for managing processing thread migration between clusters within a processor'20169,531,647'Multi-host processing'20169,525,630'Method and apparatus for assigning resources used to manage transport operations between clusters within a processor'20169,497,117'Lookup front end packet output processor'20169,391,892'Method and apparatus for managing transport operations to a cluster within a processor'20169,344,366'System and method for rule matching in a processor'20169,336,328'Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process'20169,319,316'Method and apparatus for managing transfer of transport operations from a cluster in a processor'20169,276,846'Packet extraction optimization in a network processor'20169,225,643'Lookup cluster complex'20159,141,548'Method and apparatus for managing write back cache'20159,130,819'Method and apparatus for scheduling rule matching in a processor'20159,112,767'Method and an accumulator scoreboard for out-of-order rule response handling'20159,065,860'Method and apparatus for multiple access of plural memory banks'20159,031,075'Lookup front end packet input processor'20158,995,449'Lookup cluster complex'20158,966,152'On-chip memory (OCM) physical bank parallelism'20158,954,700'Method and apparatus for managing processing thread migration between clusters within a processor'20158,923,306'Phased bucket pre-fetch in a network processor'20148,850,125'System and method to provide non-coherent access to a coherent memory system'20148,850,101'System and method to reduce memory access latencies using selective replication across multiple memory ports'20148,818,921'Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process'20148,782,287'Methods and apparatus for using multiple reassembly memories for performing multiple functions'20148,719,331'Work migration in a processor'20148,711,861'Lookup front end packet input processor'20148,606,959'Lookup front end packet output processor'20138,560,757'System and method to reduce memory access latencies using selective replication across multiple memory ports'20138,560,475'Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process'20138,472,452'Lookup cluster complex'20138,392,590'Deterministic finite automata (DFA) processing'20138,301,788'Deterministic finite automata (DFA) instruction'20127,895,431'Packet queuing, scheduling and ordering'20117,814,310'IPsec performance optimization'20107,594,081'Direct access to low-latency memory'20097,558,925'Selective replication of data structures'20097,535,907'TCP engine'20097,024,533'Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature'20066,954,770'Random number generator'20056,944,731'Dynamic random access memory system with bank conflict avoidance feature'20056,920,512'Computer architecture and system for efficient management of bi-directional bus'20056,754,739'Computer resource management and allocation system'20046,704,817'Computer architecture and system for efficient management of bi-directional bus'20046,662,265'Mechanism to track all open pages in a DRAM memory system'20036,636,955'Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature'20036,622,225'System for minimizing memory bank conflicts in a computer system'20036,591,349'Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth'20036,546,453'Proprammable DRAM address mapping mechanism'20035,333,296'Combined queue for invalidates and return data in multiprocessor system'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994Based in Clinton, MA, US· patent location history
2003–2006Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (8)· patent assignee history
2003–2014Based in Round Rock, TX, US· patent location history
2012–2018Patents assigned to CAVIUM INC (38)· patent assignee history
2012–2019Patents assigned to BOUCHARD GREGG A (20)· patent assignee history
2013–2019Patents assigned to GOYAL RAJAN (16)· patent assignee history
2013–2021Based in Georgetown, TX, US· patent location history
2019–2021Patents assigned to CAVIUM LLC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CAVIUM INC382012–2018
BOUCHARD GREGG Aself202012–2019
GOYAL RAJAN162013–2019
CAVIUM LLC92019–2021
HEWLETT PACKARD DEVELOPMENT CO82003–2006
Locations
LocationPatentsSpan
Georgetown, Texas, US452013–2021
Round Rock, Texas, US202003–2014
Clinton, Massachusetts, US11994