Inventor

David E. Miner

Inventor

Chandler, AZ, US

Overview

42→

Patents

2002–2018

Patent span

Physics

Primary field (CPC G)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing59%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use23%

B01DSeparation5%

C01BNon-metallic elements5%

C01PIndexing scheme relating to structural and physical aspects of solid inorganic compounds5%

G01RMeasuring electric variables5%

PatentTitleYear

9,892,051'Method and apparatus for use of a preload instruction to improve efficiency of cache'2018 9,086,976'Method and apparatus for associating requests and responses with identification information'2015 9,058,272'Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses'2015 8,990,505'Cache memory bank selection'2015 8,943,273'Method and apparatus for improving cache efficiency'2015 8,769,204'Programmable cache access protocol to optimize power consumption and performance'2014 8,688,919'Method and apparatus for associating requests and responses with identification information'2014 8,631,206'Way-selecting translation lookaside buffer'2014 8,533,401'Implementing direct access caches in coherent multiprocessors'2013 8,458,404'Programmable cache access protocol to optimize power consumption and performance'2013 8,296,525'Method and apparatus for data-less bus query'2012 8,135,916'Method and apparatus for hardware-configurable multi-policy coherence protocol'2012 8,065,576'Test access port'2011 7,966,477'Power optimized replay of blocked operations in a pipilined architecture'2011 7,765,349'Apparatus and method for arbitrating heterogeneous agents in on-chip busses'2010 7,757,046'Method and apparatus for optimizing line writes in cache coherent systems'2010 7,725,683'Apparatus and method for power optimized replay via selective recirculation of instructions'2010 7,685,379'Cache memory to support a processor\'s power mode of operation'2010 7,640,387'Method and apparatus for implementing heterogeneous interconnects'2009 7,634,603'System and apparatus for early fixed latency subtractive decoding'2009 7,627,797'Test access port'2009 7,487,299'Cache memory to support a processor\'s power mode of operation'2009 7,464,227'Method and apparatus for supporting opportunistic sharing in coherent multiprocessors'2008 7,428,607'Apparatus and method for arbitrating heterogeneous agents in on-chip busses'2008 7,406,553'System and apparatus for early fixed latency subtractive decoding'2008 7,406,552'Systems and methods for early fixed latency subtractive decoding including speculative acknowledging'2008 7,404,043'Cache memory to support a processor\'s power mode of operation'2008 7,366,845'Pushing of clean data to one or more processors in a system having a coherency protocol'2008 7,353,317'Method and apparatus for implementing heterogeneous interconnects'2008 7,290,093'Cache memory to support a processor\'s power mode of operation'2007 7,234,028'Power/performance optimized cache using memory write prevention through write snarfing'2007 7,219,176'System and apparatus for early fixed latency subtractive decoding'2007 7,159,077'Direct processor cache access within a system having a coherent multi-processor protocol'2007 7,143,220'Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies'2006 7,139,947'Test access port'2006 7,100,001'Methods and apparatus for cache intervention'2006 7,062,613'Methods and apparatus for cache intervention'2006 6,983,348'Methods and apparatus for cache intervention'2006 6,775,748'Methods and apparatus for transferring cache block ownership'2004 6,505,482'Nitrous oxide purification system and process'2003 6,387,161'Nitrous oxide purification system and process'2002 6,370,911'Nitrous oxide purification system and process'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2003Based in Walnut Creek, CA, US· patent location history

2004–2013Patents assigned to INTEL CORP (20)· patent assignee history

2004–2018Based in Chandler, AZ, US· patent location history

2007–2018Patents assigned to MARVELL INT LTD (19)· patent assignee history

2011–2015Patents assigned to MINER DAVID E (7)· patent assignee history

2012–2015Patents assigned to JAMIL SUJAT (7)· patent assignee history

2012–2015Patents assigned to HAMEENANTTILA TOM (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	20	2004–2013
MARVELL INT LTD	19	2007–2018
JAMIL SUJAT	7	2012–2015
MINER DAVID Eself	7	2011–2015
HAMEENANTTILA TOM	6	2012–2015

Locations

Location	Patents	Span
Chandler, AZ, US	39	2004–2018
Walnut Creek, California, US	3	2002–2003