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Inventor

John Smythe

Inventor
Boise, ID, US

Overview

119→
Patents
2000–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 119 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10BElectronic memory devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01LSemiconductor devices12%
H10NElectric solid-state devices not otherwise provided for11%
H10DInorganic electric semiconductor devices9%
C23CCoating metallic material5%
G11CStatic stores4%
H01GCapacitors3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
11,127,830Apparatus with multidielectric spacers on conductive regions of stack structures, and related methods202111,121,258Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods202111,081,364Reduction of crystal growth resulting from annealing a conductive material202110,998,221Semiconductor constructions having fluorocarbon material202110,964,536Formation of an atomic layer of germanium in an opening of a substrate material having a high aspect ratio202110,964,532Methods of forming semiconductor devices comprising silicon nitride on high aspect ratio features202110,937,654Methods of doping a silicon-containing material and methods of forming a semiconductor device202110,903,109Methods of forming high aspect ratio openings and methods of forming high aspect ratio features202110,777,562Integrated circuity, DRAM circuitry, methods used in forming integrated circuitry, and methods used in forming DRAM circuitry202010,770,465Method used in forming integrated circuitry202010,763,155Semiconductor constructions comprising dielectric material, and methods of forming dielectric fill within openings extending into semiconductor constructions202010,643,906Methods of forming a transistor and methods of forming an array of memory cells202010,504,917Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays201910,388,872Memory cell materials and semiconductor device structures201910,319,586Methods comprising an atomic layer deposition sequence201910,153,195Semiconductor constructions comprising dielectric material20189,985,049Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays20189,865,456'Methods of forming silicon nitride by atomic layer deposition and methods of forming semiconductor structures'20189,735,359'Methods of forming a memory cell material, and related methods of forming a semiconductor device structure, memory cell materials, and semiconductor device structures'20179,666,801'Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array'20179,634,250'Resistive RAM devices and methods'20179,577,186'Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells'20179,576,904'Semiconductor devices comprising interconnect structures and methods of fabrication'20179,514,976'Trench isolation implantation'20169,419,219'Resistive RAM devices and methods'20169,343,677'GCIB-treated resistive device'20169,343,665'Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array'20169,249,498'Forming memory using high power impulse magnetron sputtering'20169,214,627'Memory cell arrays'20159,142,770'Resistive RAM devices and methods'20159,123,888'Memory cells and memory cell arrays'20159,111,932'Semiconductor devices comprising interconnect structures and methods of fabrication'20159,087,989'GCIB-treated resistive device'20159,034,570'Methods of forming patterns'20158,993,044'Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials'20158,963,330'Circuit structures and electronic systems'20158,907,315'Memory cells and methods of forming memory cells'20148,861,179'Capacitors having dielectric regions that include multiple metal oxide-comprising materials'20148,853,682'Methods of self-aligned growth of chalcogenide memory access device'20148,822,974'Memory cell arrays'20148,772,166'Spacer process for on pitch contacts and related structures'20148,735,211'Resistive RAM devices and methods'20148,703,396'Methods of forming patterns'20148,691,622'Memory cells and methods of forming memory cells'20148,686,411'Methods of self-aligned growth of chalcogenide memory access device'20148,686,535'Trench isolation implantation'20148,674,336'Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays'20148,664,112'Methods for forming interconnect structures for integration of multi-layered integrated circuit devices'20148,637,113'Methods of forming a non-volatile resistive oxide memory array'20148,617,959'Resistive memory and methods of processing resistive memory'20138,614,499'Memory cell having heater material and variable resistance material embedded within insulating material'20138,598,560'Resistive memory elements exhibiting increased interfacial adhesion strength, methods of forming the same, and related resistive memory cells and memory devices'20138,575,040'Low temperature process for polysilazane oxidation/densification'20138,557,697'Vapor deposition methods for forming a metal-containing layer on a substrate'20138,536,561'Memory cells and memory cell arrays'20138,530,878'Memory arrays and methods of forming memory cells'20138,461,060'Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles'20138,455,299'Methods utilizing microwave radiation during formation of semiconductor constructions'20138,415,661'Methods of self-aligned growth of chalcogenide memory access device'20138,409,915'Methods of forming memory cells'20138,399,952'Integrated circuit devices having a strontium ruthenium oxide interface'20138,389,385'Semiconductor material manufacture'20138,349,545'Methods of forming patterns'20138,324,065'Resistive memory and methods of processing resistive memory'20128,310,807'Capacitors having dielectric regions that include multiple metal oxide-comprising materials'20128,304,353'Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors'20128,298,964'Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles'20128,283,203'Methods utilizing microwave radiation during formation of semiconductor constructions'20128,282,999'Spin-on film processing using acoustic radiation pressure'20128,241,944'Resistive RAM devices and methods'20128,236,372'Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials'20128,223,539'GCIB-treated resistive device'20128,211,743'Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes'20128,211,803'Spacer process for on pitch contacts and related structures'20128,203,179'Device having complex oxide nanodots'20128,198,124'Methods of self-aligned growth of chalcogenide memory access device'20128,193,607'Memory cell having GeN-containing material and variable resistance material embedded within insulating material'20128,133,664'Methods of forming patterns'20128,129,289'Method to deposit conformal low temperature SiO2'20128,120,184'Semiconductor constructions and methods of forming layers'20128,114,468'Methods of forming a non-volatile resistive oxide memory array'20128,048,755'Resistive memory and methods of processing resistive memory'20118,043,975'Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors'20118,034,315'Methods of forming devices comprising carbon nanotubes'20118,034,655'Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays'20117,985,617'Methods utilizing microwave radiation during formation of semiconductor constructions'20117,952,174'Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles'20117,939,442'Strontium ruthenium oxide interface'20117,927,975'Semiconductor material manufacture'20117,928,577'Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same'20117,919,829'Liner for shallow trench isolation'20117,902,084'Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors'20117,892,964'Vapor deposition methods for forming a metal-containing layer on a substrate'20117,851,307'Method of forming complex oxide nanodots for a charge trap'20107,785,978'Method of forming memory cell using gas cluster ion beams'20107,737,039'Spacer process for on pitch contacts and related structures'20107,737,559'Semiconductor constructions'20107,709,345'Trench isolation implantation'20107,659,181'Sub-micron space liner and filler process'20107,622,769'Isolation trench'20097,557,420'Low temperature process for polysilazane oxidation/densification'20097,557,047'Method of forming a layer of material using an atomic layer deposition process'20097,521,378'Low temperature process for polysilazane oxidation/densification'20097,514,366'Methods for forming shallow trench isolation'20097,501,691'Trench insulation structures including an oxide liner and oxidation barrier'20097,479,440'Method of forming an isolation structure that includes forming a silicon layer at a base of the recess'20097,439,157'Isolation trenches for memory devices'20087,273,796'Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry'20077,271,463'Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base'20077,271,464'Liner for shallow trench isolation'20077,262,135'Methods of forming layers'20077,112,513'Sub-micron space liner and densification process'20066,849,510'Non-oxidizing spacer densification method for manufacturing semiconductor devices'20056,642,112'Non-oxidizing spacer densification method for manufacturing semiconductor devices'20036,573,141'In-situ etch and pre-clean for high quality thin oxides'20036,436,195'Method of fabricating a MOS device'20026,190,973'Method of fabricating a high quality thin oxide'20016,165,846'Method of eliminating gate leakage in nitrogen annealed oxides'20006,156,653'Method of fabricating a MOS device'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2021Based in Boise, ID, US· patent location history
2003Based in Bosie, ID, US· patent location history
2006–2021Patents assigned to MICRON TECHNOLOGY INC (110)· patent assignee history
2012–2017Patents assigned to SMYTHE JOHN (35)· patent assignee history
2012–2017Patents assigned to SRINIVASAN BHASKAR (18)· patent assignee history
2012–2016Patents assigned to SANDHU GURTEJ S (16)· patent assignee history
2012–2017Patents assigned to SANDHU GURTEJ (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC1102006–2021
SMYTHE JOHNself352012–2017
SRINIVASAN BHASKAR182012–2017
SANDHU GURTEJ S162012–2016
SANDHU GURTEJ132012–2017
Locations
LocationPatentsSpan
Boise, ID, US1182000–2021
Bosie, ID, US12003