Inventor
Shumpei Kawasaki
Inventor
Tokyo, JP
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing67%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use20%
H04WWireless communication networks14%
PatentTitleYear
7,877,572'Data access in a processor for virtual machines'20117,412,581'Processor for virtual machines and method therefor'20086,996,700'Microcomputer and dividing circuit'20066,845,908'Storage card with integral file system, access control and cryptographic support'20056,748,507'Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory'20046,735,683'Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements'20046,591,294'Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals'20036,343,357'Microcomputer and dividing circuit'20026,324,634'Methods for operating logical cache memory storing logical and physical address information'20016,279,063'Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller'20016,272,620'Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation'20016,253,308'Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word'20016,223,265'Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal'20016,212,620'Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals'20016,205,535'Branch instruction having different field lengths for unconditional and conditional displacements'20016,138,226'Logical cache memory storing logical and physical address information for resolving synonym problems'20006,131,154'Microcomputer having variable bit width area for displacement'20006,122,724'Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation'20006,012,139'Microprocessor including floating point unit with 16-bit fixed length instruction set'20005,991,545'Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word'19995,987,589'Microcomputer and microcomputer system'19995,969,976'Division circuit and the division method thereof'19995,930,833'Logical cache memory storing logical and physical address information for resolving synonym problems'19995,930,523'Microcomputer having multiple bus structure coupling CPU to other processing elements'19995,832,248'Semiconductor integrated circuit having CPU and multiplier'19985,748,977'Multiply connectable microprocessor and microprocessor system'19985,682,545'Microcomputer having 16 bit fixed length instruction format'19975,608,881'Microcomputer system for accessing hierarchical buses'19975,530,965'Multiply connectable microprocessor and microprocessor system'19965,426,742'Microprocessor for supplying branch condition indicating signal in response to execution of conditional branch instruction'19955,327,543'System for selectively masking operand portions for processing thereof'19945,165,033'Microprocessor and data processor using the former'19925,043,869'Storage area structure in information processor'19915,041,969'Microprocessor and data processor using the former'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2004Patents assigned to HITACHI LTD (29)· patent assignee history
1991–2006Based in Tokyo, JP· patent location history
1996–2000Patents assigned to HITACHI MICROCOMPUTER SYST (7)· patent assignee history
1996–2004Patents assigned to HITACHI ULSI ENG CORP (7)· patent assignee history
1996–1999Based in Kodaira, JP· patent location history
1997–2002Patents assigned to HITACHI VLSI ENG (7)· patent assignee history
1999–2001Based in Palo Alto, CA, US· patent location history
2001–2002Patents assigned to HITACHI MICROCOMP SYSTEM LTD (3)· patent assignee history
2005Based in Los Altos Hills, CA, US· patent location history
2008–2011Based in Los Altos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 29 | 1991–2004 |
| HITACHI MICROCOMPUTER SYST | 7 | 1996–2000 |
| HITACHI ULSI ENG CORP | 7 | 1996–2004 |
| HITACHI VLSI ENG | 7 | 1997–2002 |
| HITACHI MICROCOMP SYSTEM LTD | 3 | 2001–2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 21 | 1991–2006 |
| Kodaira, JP | 5 | 1996–1999 |
| Palo Alto, California, US | 4 | 1999–2001 |
| Los Altos, California, US | 2 | 2008–2011 |
| Los Altos Hills, California, US | 1 | 2005 |