Inventor
THEODORUS E. STANDAERT
Inventor
US
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices24%
H10NElectric solid-state devices not otherwise provided for18%
H10BElectronic memory devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
G11CStatic stores6%
H10DInorganic electric semiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H01FMagnets2%
B82YSpecific uses or applications of nanostructures1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
12,593,468Self-aligned backside contact with increased contact area202612,543,544Backside direct contact formation202612,482,747Local interconnects having different material compositions202512,464,731Layered bottom electrode dielectric for embedded MRAM202512,453,297Recessed local interconnect semiconductor memory device202512,376,369FinFET devices202512,277,960Modified top electrode contact for MRAM embedding in advanced logic nodes202511,955,152Dielectric fill for tight pitch MRAM pillar array202411,937,514High-density memory devices using oxide gap fill202411,869,783Optimizating semiconductor binning by feed-forward process adjustment202411,837,501Selective recessing to form a fully aligned via202311,812,668Pillar-based memory hardmask smoothing and stress reduction202311,664,271Dual damascene with short liner202311,615,988FinFET devices202311,600,325Non volatile resistive memory logic device202311,569,442Dielectric retention and method of forming memory pillar202311,502,242Embedded memory devices202211,462,583Embedding magneto-resistive random-access memory devices between metal levels202211,302,630Electrode-via structure202211,257,717Selective recessing to form a fully aligned via202211,244,907Metal surface preparation for increased alignment contrast202211,239,278Bottom conductive structure with a limited top contact area202211,239,421Embedded BEOL memory device with top electrode pillar202211,223,008Pillar-based memory hardmask smoothing and stress reduction202211,217,742Bottom electrode for semiconductor memory device202211,189,693Transistor having reduced contact resistance202111,177,437Alignment through topography on intermediate component for memory device patterning202111,164,779Bamboo tall via interconnect structures202111,145,658Semiconductor structures with deep trench capacitor and methods of manufacture202111,145,813Bottom electrode for semiconductor memory device2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to IBM (26)· patent assignee history
2021–2026Based in US· patent location history
2022Patents assigned to TESSERA INC (1)· patent assignee history
2023–2025Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (2)· patent assignee history
2023Patents assigned to TESSERA LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 26 | 2021–2026 |
| ADEIA SEMICONDUCTOR SOLUTIONS LLC | 2 | 2023–2025 |
| TESSERA LLC | 2 | 2023 |
| TESSERA INC | 1 | 2022 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 30 | 2021–2026 |