LexDanaLexDanabeta
Inventor

Mark R. Visokay

Inventor
Richardson, TX, US

Overview

111→
Patents
1994–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 111 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices49%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10BElectronic memory devices13%
C23CCoating metallic material6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H01LSemiconductor devices2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
C30BSingle-crystal growth1%
B82YSpecific uses or applications of nanostructures0%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium0%
PatentTitleYear
11,004,929Trimmable silicon-based thermistor with reduced stress dependence202110,249,621Dummy contacts to mitigate plasma charging damage to gate dielectrics20198,962,350'Multi-step deposition of ferroelectric dielectric material'20158,822,236'Hydrogen-blocking film for ferroelectric capacitors'20148,575,014'Semiconductor device fabricated using a metal microstructure control process'20138,410,559'Selectively self-assembling oxygen diffusion barrier'20138,389,391'Triple-gate transistor with reverse shallow trench isolation'20138,377,790'Method of fabricating an embedded polysilicon resistor and an embedded eFuse isolated from a substrate'20138,273,645'Method to attain low defectivity fully silicided gates'20128,183,137'Use of dopants to provide low defect gate full silicidation'20128,124,529'Semiconductor device fabricated using a metal microstructure control process'20128,021,990'Gate structure and method'20117,863,192'Methods for full gate silicidation of metal gate structures'20117,842,567'Dual work function CMOS devices utilizing carbide based electrodes'20107,812,401'MOS device and process having low resistance silicide interface using additional source/drain implant'20107,767,511'Semiconductor device manufactured using a method to improve gate doping while maintaining good gate profile'20107,709,349'Semiconductor device manufactured using a gate silicidation involving a disposable chemical/mechanical polishing stop layer'20107,682,892'MOS device and process having low resistance silicide interface using additional source/drain implant'20107,678,675'Structure and method for a triple-gate transistor with reverse STI'20107,642,146'Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials'20107,629,212'Doped WGe to form dual metal gates'20097,612,422'Structure for dual work function metal gate electrodes by control of interface dipoles'20097,601,578'Defect control in gate dielectrics'20097,601,577'Work function control of metals'20097,547,596'Method of enhancing drive current in a transistor'20097,535,066'Gate structure and method'20097,531,400'Methods for fabricating MOS transistor gates with doped silicide'20097,528,024'Dual work function metal gate integration in semiconductor devices'20097,470,577'Dual work function CMOS devices utilizing carbide based electrodes'20087,432,566'Method and system for forming dual work function gate electrodes in a semiconductor device'20087,387,956'Refractory metal-based electrodes for work function setting in semiconductor devices'20087,361,599'Integrated circuit and method'20087,351,626'Method for controlling defects in gate dielectrics'20087,351,632'Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon'20087,338,865'Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation'20087,321,154'Refractory metal-based electrodes for work function setting in semiconductor devices'20087,291,890'Gate dielectric and method'20077,291,527'Work function control of metals'20077,276,408'Reduction of dopant loss in a gate structure'20077,253,102'Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers'20077,253,049'Method for fabricating dual work function metal gates'20077,253,076'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers'20077,233,035'Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound'20077,229,873'Process for manufacturing dual work function metal gates in a microelectronics device'20077,226,826'Semiconductor device having multiple work functions and method of manufacture therefor'20077,226,830'Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation'20077,183,221'Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer'20077,176,076'Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials'20077,163,880'Gate stack and gate stack etch sequence for metal gate integration'20077,148,546'MOS transistor gates with doped silicide and methods for making the same'20067,135,361'Method for fabricating transistor gate structures and gate dielectrics thereof'20067,119,386'Versatile system for triple-gated transistors with engineered corners'20067,115,530'Top surface roughness reduction of high-k dielectric materials using plasma based processes'20067,109,077'Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound'20067,105,891'Gate structure and method'20067,098,516'Refractory metal-based electrodes for work function setting in semiconductor devices'20067,071,519'Control of high-k gate dielectric film composition profile for property optimization'20067,067,434'Hydrogen free integration of high-k gate dielectrics'20067,045,456'MOS transistor gates with thin lower metal silicide and methods for making the same'20067,045,431'Method for integrating high-k dielectrics in transistor devices'20067,037,730'Capacitor with high dielectric constant materials and method of making'20067,038,263'Integrated circuits with rhodium-rich structures'20067,018,902'Gate dielectric and method'20066,979,623'Method for fabricating split gate transistor device having high-k dielectrics'20056,969,644'Versatile system for triple-gated transistors with engineered corners'20056,940,112'Integrated capacitors fabricated with conductive metal oxides'20056,936,508'Metal gate MOS transistors and methods for making the same'20056,927,106'Methods for fabricating a triple-gate MOSFET transistor'20056,918,960'CVD of PtRh with good adhesion and morphology'20056,902,939'Integrated circuit and method'20056,893,924'Dual metal-alloy nitride gate electrodes'20056,869,877'Integrated capacitors fabricated with conductive metal oxides'20056,858,908'Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide'20056,852,645'High temperature interface layer growth for high-k gate dielectric'20056,835,639'Multiple work function gates'20046,833,576'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers'20046,828,200'Multistage deposition that incorporates nitrogen via an intermediate step'20046,821,873'Anneal sequence for high- film property optimization'20046,812,112'Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers'20046,809,370'High-k gate dielectric with uniform nitrogen profile and methods for making the same'20046,809,394'Dual metal-alloy nitride gate electrodes'20046,797,599'Gate structure and method'20046,794,252'Method and system for forming dual work function gate electrodes in a semiconductor device'20046,783,997'Gate structure and method'20046,781,175'Rhodium-rich integrated circuit capacitor electrode'20046,770,521'Method of making multiple work function gates by implanting metals with metallic alloying additives'20046,767,806'METHOD OF FORMING A PATTERNED SUBSTANTIALLY CRYSTALLINE TA2O5 COMPRISING MATERIAL, AND METHOD OF FORMING A CAPACITOR HAVING A CAPACITOR DIELECTRIC REGION COMPRISING SUBSTANTIALLY CRYSTALLINE TA2O5 COMPRISING MATERIAL'20046,764,943'Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers'20046,750,126'Methods for sputter deposition of high-k dielectric films'20046,740,554'Methods to form rhodium-rich oxygen barriers'20046,696,332'Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing'20046,649,466'Method of forming DRAM circuitry'20036,642,094'Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide'20036,617,250'Methods of depositing a layer comprising tungsten and methods of forming a transistor gate line'20036,600,183'Integrated circuit capacitor and memory'20036,596,583'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers'20036,544,906'Annealing of high-k dielectric materials'20036,518,610'Rhodium-rich oxygen barriers'20036,511,896'Method of etching a substantially amorphous TA2O5 comprising layer'20036,492,241'Integrated capacitors fabricated with conductive metal oxides'20026,482,736'Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers'20026,444,542'Integrated circuit and method'20026,380,080'Methods for preparing ruthenium metal films'20026,326,293'Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation'20016,211,034'Metal patterning with adhesive hardmask layer'20016,211,035'Integrated circuit and method'20016,159,835'Encapsulated low resistance gate structure and method for forming same'20006,090,697'Etchstop for integrated circuits'20005,972,722'Adhesion promoting sacrificial etch stop layer in advanced capacitor structures'19995,603,766'Method for producing uniaxial tetragonal thin films of ternary intermetallic compounds'19975,363,794'Uniaxial thin film structures formed from oriented bilayers and multilayers'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–1997Based in Stanford, CA, US· patent location history
1999–2021Patents assigned to TEXAS INSTRUMENTS INC (86)· patent assignee history
1999–2021Based in Dallas, TX, US· patent location history
2001–2008Based in Boise, ID, US· patent location history
2002–2007Patents assigned to MICRON TECHNOLOGY INC (20)· patent assignee history
2002–2012Based in Richardson, TX, US· patent location history
2009–2013Based in Wappingers Falls, NY, US· patent location history
2012–2013Patents assigned to VISOKAY MARK R (5)· patent assignee history
2012–2013Patents assigned to CHAMBERS JAMES J (3)· patent assignee history
2012–2013Patents assigned to COLOMBO LUIGI (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC861999–2021
MICRON TECHNOLOGY INC202002–2007
VISOKAY MARK Rself52012–2013
CHAMBERS JAMES J32012–2013
COLOMBO LUIGI22012–2013
Locations
LocationPatentsSpan
Richardson, Texas, US842002–2012
Dallas, Texas, US101999–2021
Wappingers Falls, New York, US72009–2013
Boise, ID, US72001–2008
Stanford, California, US21994–1997