Inventor
Chi Chang
Inventor
Saratoga, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices33%
H10DInorganic electric semiconductor devices27%
B60KArrangement or mounting of propulsion units or of transmissions in vehicles7%
H01LSemiconductor devices7%
F16HGearing4%
G11CStatic stores4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
F01PCooling of machines or engines in general2%
F02BInternal-combustion piston engines2%
F02DControlling combustion engines2%
PatentTitleYear
9,917,211'Flash memory cells having trenched storage elements'20189,551,268'Cooling air intake device for vehicle'20179,461,151'Dual storage node memory'20169,303,749'Vehicle power switching device'20169,159,568'Method for fabricating memory cells having split charge storage nodes'20159,121,353'Control structure of engine throttle valve'20159,046,065'Vehicle air intake mechanism'20158,900,081'Vehicle power switching device'20148,742,486'Flash memory cells having trenched storage elements'20148,720,635'Vehicle having two generators'20148,564,042'Dual storage node memory'20138,455,268'Gate replacement with top oxide regrowth for the top oxide improvement'20138,183,623'Dual charge storage node memory device and methods for fabricating such device'20128,076,712'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'20117,915,123'Dual charge storage node memory device and methods for fabricating such device'20117,785,965'Dual storage node memory devices and methods for fabricating the same'20107,767,517'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'20107,671,403'P-channel NAND in isolated N-well'20107,288,809'Flash memory with buried bit lines'20076,974,995'Method and system for forming dual gate structures in a nonvolatile memory using a protective layer'20056,368,912'Method of fabricating an isolation structure between a vertical transistor and a deep trench capacitor'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002Based in Taipei, TW· patent location history
2005–2018Patents assigned to SPANSION LLC (12)· patent assignee history
2005–2016Based in Redwood City, CA, US· patent location history
2010–2018Based in Saratoga, CA, US· patent location history
2011–2015Patents assigned to CHANG CHI (6)· patent assignee history
2011–2015Patents assigned to KINOSHITA HIROYUKI (5)· patent assignee history
2011–2015Patents assigned to LEE CHUNGHO (5)· patent assignee history
2014–2017Patents assigned to KWANG YANG MOTOR CO (6)· patent assignee history
2014–2017Based in Kaohsiung, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPANSION LLC | 12 | 2005–2018 |
| CHANG CHIself | 6 | 2011–2015 |
| KWANG YANG MOTOR CO | 6 | 2014–2017 |
| KINOSHITA HIROYUKI | 5 | 2011–2015 |
| LEE CHUNGHO | 5 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 11 | 2010–2018 |
| Kaohsiung, TW | 6 | 2014–2017 |
| Redwood City, California, US | 3 | 2005–2016 |
| Taipei, TW | 1 | 2002 |