Inventor
Arthur D. Tuminaro
Inventor
Lagrangeville, NY, US
Overview
Patents· 10 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores90%
H03KPulse technique10%
PatentTitleYear
8,233,331'Single clock dynamic compare circuit'20127,463,537'Global bit select circuit interface with dual read and write bit line pairs'20087,336,546'Global bit select circuit with dual read and write bit line pairs'20087,272,030'Global bit line restore timing scheme and circuit'20077,170,774'Global bit line restore timing scheme and circuit'20077,113,433'Local bit select with suppression of fast read before write'20067,006,403'Self timed bit and read/write pulse stretchers'20066,958,943'Programmable sense amplifier timing generator'20055,627,484'CMOS sense amplifier'19975,239,506'Latch and data out driver for memory arrays'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2012Patents assigned to IBM (10)· patent assignee history
1993–2012Based in Lagrangeville, NY, US· patent location history
2012Patents assigned to CHAN YUEN H (1)· patent assignee history
2012Patents assigned to PELELLA ANTONIO R (1)· patent assignee history
2012Patents assigned to SERTON RICHARD E (1)· patent assignee history
2012Patents assigned to TUMINARO ARTHUR (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 10 | 1993–2012 |
| CHAN YUEN H | 1 | 2012 |
| PELELLA ANTONIO R | 1 | 2012 |
| SERTON RICHARD E | 1 | 2012 |
| TUMINARO ARTHURself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Lagrangeville, New York, US | 10 | 1993–2012 |