Inventor
Narayanan Iyer
Inventor
Schenectady, NY, US
Overview
Patents· 3 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing50%
B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering25%
G05BControl or regulating systems in general25%
PatentTitleYear
10,884,394Additive manufacturing machine calibration based on a test-page based object20216,976,131'Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system'20056,463,494'Method and system for implementing control signals on a low pin count bus'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2005Patents assigned to INTEL CORP (2)· patent assignee history
2002Based in Davis, CA, US· patent location history
2005Based in Folsom, CA, US· patent location history
2021Patents assigned to GEN ELECTRIC (1)· patent assignee history
2021Based in Schenectady, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 2 | 2002–2005 |
| GEN ELECTRIC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Schenectady, New York, US | 1 | 2021 |
| Folsom, California, US | 1 | 2005 |
| Davis, California, US | 1 | 2002 |