Inventor

Junichi Shiozawa

Inventor
Yokkaichi, JP

Overview

16→
Patents
1989–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 16 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices44%
H10DInorganic electric semiconductor devices31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
B23QDetails, components, or accessories for machine tools, e.g. arrangements for copying or controlling3%
C23CCoating metallic material3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
8,728,903'Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode'20148,404,537'Method of manufacturing semiconductor device'20138,258,568'Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode'20128,097,503'Method of manufacturing semiconductor device'20127,927,949'Semiconductor memory device and method of manufacturing the same'20117,928,530'Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode'20117,858,467'Method of manufacturing semiconductor device'20107,723,772'Semiconductor memory device and method of manufacturing the same'20107,679,127'Semiconductor device and method of manufacturing the same'20107,645,674'Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode'20107,315,073'Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode'20086,803,622'Semiconductor device and method of manufacturing the same'20045,670,805'Controlled recrystallization of buried strap in a semiconductor memory device'19975,543,348'Controlled recrystallization of buried strap in a semiconductor memory device'19965,389,570'Method of forming boron doped silicon layer and semiconductor'19954,887,345'Turret apparatus'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2014Patents assigned to TOSHIBA KK (15)· patent assignee history
1995Based in Tokyo, JP· patent location history
1996–1997Patents assigned to IBM (2)· patent assignee history
1996–1997Based in Wappingers Falls, NY, US· patent location history
2004–2010Based in Mie, JP· patent location history
2008–2014Based in Yokkaichi, JP· patent location history
2010–2013Based in Yokohama, JP· patent location history
2012–2014Patents assigned to SHIOZAWA JUNICHI (4)· patent assignee history
2012–2013Patents assigned to KAMIOKA ISAO (2)· patent assignee history
2012–2013Patents assigned to KATO RYU (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK151995–2014
SHIOZAWA JUNICHIself42012–2014
IBM21996–1997
KAMIOKA ISAO22012–2013
KATO RYU22012–2013
Locations
LocationPatentsSpan
Yokkaichi, JP72008–2014
Yokohama, JP32010–2013
Mie, JP22004–2010
Wappingers Falls, New York, US21996–1997
Tokyo, JP11995