Inventor

Rahul Sharangpani

Inventor

Fremont, CA, US

Overview

1998–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 67 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices25%

H10BElectronic memory devices25%

H10DInorganic electric semiconductor devices21%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

G11CStatic stores4%

H10NElectric solid-state devices not otherwise provided for1%

B05DProcesses for applying fluent materials to surfaces, in general0%

B82YSpecific uses or applications of nanostructures0%

C23CCoating metallic material0%

PatentTitleYear

11,127,728Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same2021 11,121,140Ferroelectric tunnel junction memory device with integrated ovonic threshold switches2021 11,114,534Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same2021 11,049,880Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same2021 11,024,648Ferroelectric memory devices including a stack of ferroelectric and antiferroelectric layers and method of making the same2021 10,937,809Three-dimensional memory device containing ferroelectric memory elements encapsulated by transition metal nitride materials and method of making thereof2021 10,868,025Three-dimensional memory device including replacement crystalline channels and methods of making the same2020 10,804,291Three-dimensional memory device using epitaxial semiconductor channels and a buried source line and method of making the same2020 10,797,060Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same2020 10,797,061Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same2020 10,790,300Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same2020 10,756,110Method of forming seamless drain-select-level electrodes for a three-dimensional memory device and structures formed by the same2020 10,741,572Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method of making the same2020 10,665,581Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same2020 10,651,196Three-dimensional multilevel device containing seamless unidirectional metal layer fill and method of making same2020 10,622,368Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof2020 10,615,123Three-dimensional memory device containing compositionally graded word line diffusion barrier layer for and methods of forming the same2020 10,529,620Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same2020 10,381,364Three-dimensional memory device including vertically offset drain select level layers and method of making thereof2019 10,381,559Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same2019 10,381,409Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same2019 10,361,213Three dimensional memory device containing multilayer wordline barrier films and method of making thereof2019 10,355,139Three-dimensional memory device with amorphous barrier layer and method of making thereof2019 10,290,648Three-dimensional memory device containing air gap rails and method of making thereof2019 10,290,652Three-dimensional memory device with graded word lines and methods of making the same2019 10,283,513Three-dimensional memory device with annular blocking dielectrics and method of making thereof2019 10,276,583Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof2019 10,128,261Cobalt-containing conductive layers for control gate electrodes in a memory structure2018 10,050,054Three-dimensional memory device having drain select level isolation structure and method of making thereof2018 9,984,963Cobalt-containing conductive layers for control gate electrodes in a memory structure2018 9,960,180Three-dimensional memory device with partially discrete charge storage regions and method of making thereof2018 9,893,081'Ridged word lines for increasing control gate lengths in a three-dimensional memory device'2018 9,875,929Three-dimensional memory device with annular blocking dielectrics and discrete charge storage elements and method of making thereof2018 9,842,857'Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices'2017 9,842,907'Memory device containing cobalt silicide control gate electrodes and method of making thereof'2017 9,824,966'Three-dimensional memory device containing a lateral source contact and method of making the same'2017 9,812,463'Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof'2017 9,806,090'Vertical floating gate NAND with selectively deposited ALD metal films'2017 9,806,089'Method of making self-assembling floating gate electrodes for a three-dimensional memory device'2017 9,793,139'Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines'2017 9,768,270'Method of selectively depositing floating gate material in a memory device'2017 9,754,820'Three-dimensional memory device containing an aluminum oxide etch stop layer for backside contact structure and method of making thereof'2017 9,698,223'Memory device containing stress-tunable control gate electrodes'2017 9,698,152'Three-dimensional memory structure with multi-component contact via structure and method of making thereof'2017 9,691,884'Monolithic three dimensional NAND strings and methods of fabrication thereof'2017 9,659,955'Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure'2017 9,646,990'NAND memory strings and methods of fabrication thereof'2017 9,613,977'Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices'2017 9,576,966'Cobalt-containing conductive layers for control gate electrodes in a memory structure'2017 9,570,455'Metal word lines for three dimensional memory devices'2017 9,530,785'Three-dimensional memory devices having a single layer channel and methods of making thereof'2016 9,524,977'Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure'2016 9,515,079'Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack'2016 9,496,419'Ruthenium nucleation layer for control gate electrodes in a memory structure'2016 9,484,357'Selective blocking dielectric formation in a three-dimensional memory structure'2016 9,478,558'Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer'2016 9,397,046'Fluorine-free word lines for three-dimensional memory devices'2016 9,379,132'NAND memory strings and methods of fabrication thereof'2016 9,379,124'Vertical floating gate NAND with selectively deposited ALD metal films'2016 9,305,849'Method of making a three dimensional NAND device'2016 9,236,396'Three dimensional NAND device and method of making thereof'2016 9,230,983'Metal word lines for three dimensional memory devices'2016 9,159,739'Floating gate ultrahigh density vertical NAND flash memory'2015 7,847,341'Electron blocking layers for electronic devices'2010 6,303,524'High temperature short time curing of low dielectric constant materials using rapid thermal processing techniques'2001 5,980,637'System for depositing a material on a substrate using light energy'1999 5,820,942'Process for depositing a material on a substrate using light energy'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998Patents assigned to ASSOCIATES AG (1)· patent assignee history

1998–1999Based in Clemson, SC, US· patent location history

2001Patents assigned to MATTSON THERMAL PRODUCTS INC (1)· patent assignee history

2001–2021Based in Fremont, CA, US· patent location history

2010Patents assigned to NANOSYS INC (1)· patent assignee history

2015–2018Patents assigned to SANDISK TECHNOLOGIES INC (25)· patent assignee history

2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (57)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SANDISK TECHNOLOGIES LLC	57	2016–2021
SANDISK TECHNOLOGIES INC	25	2015–2018
ASSOCIATES AG	1	1998
MATTSON THERMAL PRODUCTS INC	1	2001
NANOSYS INC	1	2010

Locations

Location	Patents	Span
Fremont, California, US	65	2001–2021
Clemson, SC, US	2	1998–1999