Inventor

Li-Kong Wang

Inventor

Montvale, NJ, US

Overview

1984–2013

Patent span

Electricity

Primary field (CPC H)

Patents· 83 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores15%

H10DInorganic electric semiconductor devices14%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

G06FElectric digital data processing8%

H10BElectronic memory devices8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

H05KPrinted circuits4%

Y10TTechnical subjects covered by former us classification4%

H03KPulse technique3%

PatentTitleYear

8,495,444'Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components'2013 7,778,351'Tunable CMOS receiver apparatus'2010 7,475,320'Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components'2009 7,447,273'Redundancy structure and method for high-speed serial link'2008 7,355,872'Segmented content addressable memory architecture for improved cycle time and reduced power consumption'2008 7,216,284'Content addressable memory having reduced power consumption'2007 7,191,371'System and method for sequential testing of high speed serial link core'2007 7,176,107'Hybrid substrate and method for fabricating the same'2007 7,112,502'Method to fabricate passive components using conductive polymer'2006 7,088,074'System level device for battery and integrated circuit integration'2006 7,052,937'Method and structure for providing improved thermal conduction for silicon semiconductor devices'2006 7,041,525'Three-dimensional island pixel photo-sensor'2006 7,029,956'Memory system capable of operating at high temperatures and method for fabricating the same'2006 7,023,528'Hybrid electronic mask'2006 7,005,744'Conductor line stack having a top portion of a second layer that is smaller than the bottom portion'2006 6,994,903'Hybrid substrate and method for fabricating the same'2006 6,958,522'Method to fabricate passive components using conductive polymer'2005 6,941,414'High speed embedded DRAM with SRAM-like interface'2005 6,911,354'Polymer thin-film transistor with contact etch stops'2005 6,911,375'Method of fabricating silicon devices on sapphire with wafer bonding at low temperature'2005 6,910,165'Digital random noise generator'2005 6,894,916'Memory array employing single three-terminal non-volatile storage elements'2005 6,864,504'Planar polymer transistor'2005 6,825,534'Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate'2004 6,823,293'Hierarchical power supply noise monitoring device and system for very large scale integrated circuits'2004 6,818,487'Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof'2004 6,803,805'Distributed DC voltage generator for system on chip'2004 6,781,185'Semiconductor high dielectric constant decoupling capacitor structures and process for fabrication'2004 6,777,286'Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating'2004 6,768,063'Structure and method for shadow mask electrode'2004 6,751,151'Ultra high-speed DDP-SRAM cache'2004 6,744,087'Non-volatile memory using ferroelectric gate field-effect transistors'2004 6,737,907'Programmable DC voltage generator system'2004 6,728,916'Hierarchical built-in self-test for system-on-chip design'2004 6,720,595'Three-dimensional island pixel photo-sensor'2004 6,697,909'Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory'2004 6,670,234'Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof'2003 6,664,576'Polymer thin-film transistor with contact etch stops'2003 6,649,935'Self-aligned, planarized thin-film transistors, devices employing the same'2003 6,649,959'Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby'2003 6,629,291'Integrated power solution for system on chip applications'2003 6,627,924'Memory system capable of operating at high temperatures and method for fabricating the same'2003 6,624,526'Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating'2003 6,620,657'Method of forming a planar polymer transistor using substrate bonding techniques'2003 6,621,294'Pad system for an integrated circuit or device'2003 6,614,714'Semiconductor memory system having a data clock system for reliable high-speed data transfers'2003 6,611,033'Micromachined electromechanical (MEM) random access memory array and method of making same'2003 6,603,690'Low-power static column redundancy scheme for semiconductor memories'2003 6,603,683'Decoding scheme for a stacked bank architecture'2003 6,594,196'Multi-port memory device and system for addressing the multi-port memory device'2003 6,579,743'Chip packaging system and method using deposited diamond film'2003 6,573,565'Method and structure for providing improved thermal conduction for silicon semiconductor devices'2003 6,556,477'Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same'2003 6,542,973'Integrated redundancy architecture system for an embedded DRAM'2003 6,529,402'Low power static memory'2003 6,512,683'System and method for increasing the speed of memories'2003 6,504,777'Enhanced bitline equalization for hierarchical bitline architecture'2003 6,504,173'Dual gate FET and process'2003 6,492,227'Method for fabricating flash memory device using dual damascene process'2002 6,469,949'Fuse latch array system for an embedded DRAM having a micro-cell architecture'2002 6,452,110'Patterning microelectronic features without using photoresists'2002 6,437,623'Data retention registers'2002 6,434,076'Refresh control circuit for low-power SRAM applications'2002 6,426,903'Redundancy arrangement using a focused ion beam'2002 6,411,157'Self-refresh on-chip voltage generator'2002 6,400,619'Micro-cell redundancy scheme for high performance eDRAM'2002 6,389,505'Restore tracking system for DRAM'2002 6,358,791'Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby'2002 6,356,134'Universal clock generator circuit and adjustment method for providing a plurality of clock frequencies'2002 6,355,531'Method for fabricating semiconductor devices with different properties using maskless process'2002 6,349,067'System and method for preventing noise cross contamination between embedded DRAM and system chip'2002 6,337,513'Chip packaging system and method using deposited diamond film'2002 6,307,805'High performance semiconductor memory device with low power consumption'2001 6,278,184'Solder disc connection'2001 6,271,111'High density pluggable connector array and process thereof'2001 6,253,986'Solder disc connection'2001 6,214,653'Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate'2001 6,207,530'Dual gate FET and process'2001 6,198,677'Boosted sensing ground circuit'2001 6,070,321'Solder disc connection'2000 5,782,403'Ultrasonic chip removal method and apparatus'1998 5,675,164'High performance multi-mesa field effect transistor'1997 4,435,895'Process for forming complementary integrated circuit devices'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1984Patents assigned to BELL TELEPHONE LABOR INC (1)· patent assignee history

1997–2013Patents assigned to IBM (82)· patent assignee history

1997–2013Based in Montvale, NJ, US· patent location history

1998Based in Manassas, VA, US· patent location history

2000–2001Based in Poughkeepsie, NY, US· patent location history

2001–2004Based in Mount Vale, NJ, US· patent location history

2006Based in Lagrangeville, NY, US· patent location history

2013Patents assigned to KNEBEL DANIEL R (1)· patent assignee history

2013Patents assigned to REOHR WILLIAM ROBERT (1)· patent assignee history

2013Patents assigned to WANG LI-KONG (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	82	1997–2013
BELL TELEPHONE LABOR INC	1	1984
KNEBEL DANIEL R	1	2013
REOHR WILLIAM ROBERT	1	2013
WANG LI-KONGself	1	2013

Locations

Location	Patents	Span
Montvale, New Jersey, US	72	1997–2013
Mount Vale, New Jersey, US	4	2001–2004
Poughkeepsie, New York, US	4	2000–2001
Lagrangeville, New York, US	1	2006
Manassas, Virginia, US	1	1998