LexDanaLexDanabeta
Inventor

Jeng-Bang Yau

Inventor
Yorktown Heights, NY, US

Overview

105→
Patents
2010–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 105 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G01TMeasurement of nuclear or x-radiation4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
H10BElectronic memory devices4%
G11CStatic stores3%
B82YSpecific uses or applications of nanostructures2%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
PatentTitleYear
11,101,219Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements202111,061,146Nanosheet radiation dosimeter202111,018,225III-V extension by high temperature plasma doping202110,879,202System and method for forming solder bumps202010,839,909Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array202010,784,347High-performance lateral BJT with epitaxial lightly doped intrinsic base202010,777,555Low voltage (power) junction FET with all-around junction gate202010,741,645Thin-base high frequency lateral bipolar junction transistor202010,734,505Lateral bipolar junction transistor with dual base region202010,707,336High-performance lateral BJT with epitaxial lightly doped intrinsic base202010,629,730Body contact in Fin field effect transistor design202010,573,648Low voltage (power) junction FET with all-around junction gate202010,553,708Twin gate tunnel field-effect transistor (FET)202010,553,586Stacked complementary junction FETs for analog electronic circuits202010,483,368Single crystalline extrinsic bases for bipolar junction structures201910,468,503Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices201910,381,349Stacked complementary junction FETs for analog electronic circuits201910,319,442Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array201910,312,151Monolithic co-integration of MOSFET and JFET for neuromorphic/cognitive circuit applications201910,283,516Stacked nanosheet field effect transistor floating-gate EEPROM cell and array201910,269,714Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements201910,236,366Semiconductor-on-insulator lateral heterojunction bipolar transistor having epitaxially grown intrinsic base and deposited extrinsic base201910,224,403Thin-base high frequency lateral bipolar junction transistor201910,170,186High-density EEPROM arrays utilizing stacked field effect transistors201910,134,882Method of junction control for lateral bipolar junction transistor201810,128,343III-V MOSFET with self-aligned diffusion barrier201810,115,750Sensors including complementary lateral bipolar junction transistors201810,079,228Tight integrated vertical transistor dual diode structure for electrostatic discharge circuit protector201810,074,734Germanium lateral bipolar transistor with silicon passivation201810,056,379Low voltage (power) junction FET with all-around junction gate201810,049,742Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array201810,043,711Contact resistance reduction by III-V Ga deficient surface201810,026,752Stacked SOI lateral bipolar transistor RF power amplifier and driver201810,026,733Complementary SOI lateral bipolar transistors with backplate bias201810,008,281One time programmable read-only memory (ROM) in SOI CMOS20189,997,619Bipolar junction transistors and methods forming same20189,947,755III-V MOSFET with self-aligned diffusion barrier20189,947,649Large area electrostatic dischage for vertical transistor structures20189,947,677High-density EEPROM arrays having parallel-connected common-floating-gate NFET and PFET as memory cell20189,929,258'Method of junction control for lateral bipolar junction transistor'20189,887,278'Semiconductor-on-insulator lateral heterojunction bipolar transistor having epitaxially grown intrinsic base and deposited extrinsic base'20189,887,264'Nanowire field effect transistor (FET) and method for fabricating the same'20189,853,109III-V MOSFET with self-aligned diffusion barrier20179,852,938Passivated germanium-on-insulator lateral bipolar transistors20179,799,756'Germanium lateral bipolar transistor with silicon passivation'20179,726,631'Ultra-sensitive biosensor based on lateral bipolar junction transistor having self-aligned epitaxially grown base'20179,704,569'One time programmable read-only memory (ROM) in SOI CMOS'20179,691,886'Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base'20179,679,967'Contact resistance reduction by III-V Ga deficient surface'20179,659,655'Memory arrays using common floating gate series devices'20179,659,979'Sensors including complementary lateral bipolar junction transistors'20179,647,099'Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base'20179,625,409'Ultra-sensitive biosensor based on lateral bipolar junction transistor having self-aligned epitaxially grown base'20179,614,148'Magnetic-field and magnetic-field gradient sensors based on lateral SOI bipolar transistors'20179,589,791'Compound finFET device including oxidized III-V fin isolator'20179,564,429'Lateral bipolar sensor with sensing signal amplification'20179,548,238'Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same'20179,548,355'Compound finFET device including oxidized III-V fin isolator'20179,536,788'Complementary SOI lateral bipolar transistors with backplate bias'20179,515,198'Magnetic-field and magnetic-field gradient sensors based on lateral SOI bipolar transistors'20169,502,504'SOI lateral bipolar transistors having surrounding extrinsic base portions'20169,496,347'Graded buffer epitaxy in aspect ratio trapping'20169,437,718'Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap emitter/collector which are epitaxially grown'20169,431,301'Nanowire field effect transistor (FET) and method for fabricating the same'20169,405,017'Ultra-sensitive radiation dosimeters'20169,385,122'Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same'20169,377,543'Charge sensors using inverted lateral bipolar junction transistors'20169,379,028'SOI CMOS structure having programmable floating backplate'20169,331,097'High speed bipolar junction transistor for high voltage applications'20169,318,585'Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap emitter/collector which are epitaxially grown'20169,318,555'Fabrication of graphene nanoelectronic devices on SOI structures'20169,240,326'Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact'20169,184,290'Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer'20159,177,956'Field effect transistor (FET) with self-aligned contacts, integrated circuit (IC) chip and method of manufacture'20159,170,338'Charge sensors using inverted lateral bipolar junction transistors'20159,064,776'Radiation hardened transistors based on graphene and carbon nanotubes'20159,059,205'Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same'20159,059,095'Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact'20159,059,195'Lateral bipolar transistors having partially-depleted intrinsic base'20159,040,929'Charge sensors using inverted lateral bipolar junction transistors'20158,980,667'Charge sensors using inverted lateral bipolar junction transistors'20158,962,436'Lateral bipolar transistors having partially-depleted intrinsic base'20158,912,030'Method for radiation monitoring'20148,895,995'Lateral silicon-on-insulator bipolar junction transistor radiation dosimeter'20148,877,606'Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation'20148,803,131'Metal-free integrated circuits comprising graphene and carbon nanotubes'20148,796,668'Metal-free integrated circuits comprising graphene and carbon nanotubes'20148,673,703'Fabrication of graphene nanoelectronic devices on SOI structures'20148,614,111'Fully depleted silicon on insulator neutron detector'20138,586,426'Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box'20138,587,063'Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels'20138,580,635'Method of replacing silicon with metal in integrated circuit chip fabrication'20138,546,246'Radiation hardened transistors based on graphene and carbon nanotubes'20138,492,838'Isolation structures for SOI devices with ultrathin SOI and ultrathin box'20138,476,683'On-chip radiation dosimeter'20138,455,861'Graphene based switching device having a tunable bandgap'20138,450,198'Graphene based switching device having a tunable bandgap'20138,361,829'On-chip radiation dosimeter'20138,227,865'Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer'20128,212,218'Dosimeter powered by passive RF absorption'20128,105,928'Graphene based switching device having a tunable bandgap'20128,080,805'FET radiation monitor'20118,030,145'Back-gated fully depleted SOI transistor'20117,767,546'Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer'20107,684,147'Magnetoelectronic devices based on colossal magnetoresistive thin films'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2021Patents assigned to IBM (97)· patent assignee history
2010–2014Based in Ossining, NY, US· patent location history
2010Based in Hamden, CT, US· patent location history
2011–2016Patents assigned to YAU JENG-BANG (23)· patent assignee history
2011–2021Based in Yorktown Heights, NY, US· patent location history
2012–2016Patents assigned to LIN YU-MING (9)· patent assignee history
2012–2016Patents assigned to DENNARD ROBERT H (6)· patent assignee history
2015–2017Patents assigned to GLOBALFOUNDRIES INC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM972010–2021
YAU JENG-BANGself232011–2016
GLOBALFOUNDRIES INC92015–2017
LIN YU-MING92012–2016
DENNARD ROBERT H62012–2016
Locations
LocationPatentsSpan
Yorktown Heights, New York, US992011–2021
Ossining, New York, US52010–2014
Hamden, CT, US12010