Inventor
ERIC N. LEE
Inventor
US
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores49%
G06FElectric digital data processing33%
H01LSemiconductor devices5%
H10BElectronic memory devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
12,585,583Multiple write programming for a segment of a memory device202612,505,897Program refresh with gate-induced drain leakage202512,444,453Volatile data storage in NAND memory202512,411,631Status polling based on die-generated pulsed signal202512,387,781Corrective reads with improved recovery from data retention loss202512,387,790Double single level cell program in a memory device202512,373,109Validating read level voltage in memory devices202512,354,982Memory devices with backside bond pads under a memory array202512,340,126Workload-based scan optimization202512,334,142Sacrificial strings in a memory device to detect read disturb202512,334,153Adaptive pre-read management in multi-pass programming202512,334,154Write-once memory encoded data202512,334,163Single-level cell program-verify, latch-limited data recovery202512,307,090Memory device programming technique for increased bits per cell202512,300,332Resumption of program or erase operations in memory202512,266,407Conditional valley tracking during corrective reads202512,249,364Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same202512,248,411Data burst queue management202512,237,018Memory sub-system sanitization202512,217,799Parallelized defect detection across multiple sub-blocks in a memory device202512,182,046Data burst suspend mode using pause detection202412,142,343Memory devices for multiple read operations202412,131,060Quick charge loss mitigation using two-pass controlled delay202412,111,781Data burst suspend mode using multi-level signaling202412,105,967Two-tier defect scan management202412,073,891Integrated command to calibrate read voltage level202412,073,895Ganged single level cell verify in a memory device202412,061,806Second read initialization on latch-limited memory device202412,019,550Concurrent page cache resource access in a multi-plane memory device202411,977,778Workload-based scan optimization202411,972,135Status polling based on die-generated pulsed signal202411,960,722Memory device programming technique for increased bits per cell202411,935,853Memory devices with backside bond pads under a memory array202411,830,551Memory plane access management202311,810,621Memory sub-system sanitization202311,763,900Resumption of program or erase operations in memory202311,756,594Memory devices for multiple read operations202311,742,034Memory device including dynamic programming voltage202311,735,268Memory devices for suspend and resume operations202311,669,456Cache release command for cache reads in a memory sub-system202311,664,079Intervallic dynamic start voltage and program verify sampling in a memory sub-system202311,653,499Semiconductor devices including staircase structures202311,636,904Almost ready memory management202311,568,933Memory plane access management202311,462,281Intervallic dynamic start voltage and program verify sampling in a memory sub-system202211,456,039Resumption of program or erase operations in memory202211,410,949Memory devices with backside bond pads under a memory array202211,367,473Wave pipeline202211,335,418Memory device including dynamic programming voltage202211,238,937Apparatus for programming memory cells using multi-step programming pulses202211,217,310Memory devices with distributed block select for a vertical string driver tile architecture202211,188,473Cache release command for cache reads in a memory sub-system2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (50)· patent assignee history
2021–2026Based in US· patent location history
2024–2025Patents assigned to LODESTAR LICENSING GROUP LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 50 | 2021–2026 |
| LODESTAR LICENSING GROUP LLC | 2 | 2024–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 52 | 2021–2026 |