Inventor

Wen-Jeng Lin

Inventor

Pan-Chiao, TW

Overview

20→

Patents

1996–2009

Patent span

Electricity

Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices23%

H10DInorganic electric semiconductor devices21%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests15%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%

C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds10%

D01FChemical features in the manufacture of artificial filaments, threads, fibres, bristles or ribbons5%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form3%

C23CCoating metallic material3%

C30BSingle-crystal growth3%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%

PatentTitleYear

7,638,390'Manufacturing method of static random access memory'2009 7,449,741'SRAM cell structure and manufacturing method thereof'2008 7,358,556'SRAM cell structure and manufacturing method thereof'2008 7,309,890'SRAM cell structure and manufacturing method thereof'2007 7,157,763'SRAM cell structure and manufacturing method thereof'2007 7,144,777'Non-volatile memory and manufacturing method thereof'2006 6,689,673'Method for forming a gate with metal silicide'2004 6,306,760'Method of forming a self-aligned contact hole on a semiconductor wafer'2001 6,281,134'Method for combining logic circuit and capacitor'2001 6,255,231'Method for forming a gate oxide layer'2001 6,238,958'Method for forming a transistor with reduced source/drain series resistance'2001 6,221,767'Method of fabricating a silicide landing pad'2001 6,218,239'Manufacturing method of a bottom plate'2001 6,180,514'Method for forming interconnect using dual damascene'2001 6,177,297'Method of forming metallic fuse demanding lower laser power for circuit repair'2001 5,946,568'Self aligned method of fabricating a DRAM with improved capacitance'1999 5,891,987'Copolyamide composition with a high glass transition temperature'1999 5,760,167'Copolyamide composition with a high glass transition temperature and a low melting point'1998 5,519,108'Catalytic compositions containing tetrabutyl titanate and a mixture of cocatalysts for the preparation of poly(butylene terephthalate)'1996 5,516,879'Catalytic compositions for the preparation of poly(butylene terephthalate)'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–1999Patents assigned to IND TECH RES INST (4)· patent assignee history

1996–2001Based in Hsinchu, TW· patent location history

1999Patents assigned to MOSEL VITELIC INC (1)· patent assignee history

1999Based in Taipei, TW· patent location history

2001–2008Patents assigned to UNITED MICROELECTRONICS CORP (11)· patent assignee history

2001Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history

2001–2009Based in Pan-Chiao, TW· patent location history

2001Based in Pan Chiao, TW· patent location history

2009Patents assigned to UNITED MICROELECTRIC CORP (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
UNITED MICROELECTRONICS CORP	11	2001–2008
IND TECH RES INST	4	1996–1999
MOSEL VITELIC INC	1	1999
TAIWAN SEMICONDUCTOR MFG	1	2001
UNITED MICROELECTRIC CORP	1	2009

Locations

Location	Patents	Span
Pan-Chiao, TW	13	2001–2009
Hsinchu, TW	5	1996–2001
Pan Chiao, TW	1	2001
Taipei, TW	1	1999