Inventor
Kazushi Amanuma
Inventor
Tokyo, JP
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices43%
H10DInorganic electric semiconductor devices43%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
PatentTitleYear
6,603,203'Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same'20036,395,612'Semiconductor device and method of manufacturing the same'20026,323,510'Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45.degree. angles'20016,316,801'Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same'20016,281,536'Ferroelectric memory device with improved ferroelectric capacity characteristic'20016,188,098'Semiconductor device and method of manufacturing the same'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2002Patents assigned to NEC CORP (5)· patent assignee history
2001–2002Patents assigned to SYMETRIX CORP (2)· patent assignee history
2001–2003Based in Tokyo, JP· patent location history
2003Patents assigned to NEC ELECTRONICS CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 5 | 2001–2002 |
| SYMETRIX CORP | 2 | 2001–2002 |
| NEC ELECTRONICS CORP | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 6 | 2001–2003 |