Inventor
Vasant Rao
Inventor
Fishkill, NY, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing96%
G01RMeasuring electric variables4%
PatentTitleYear
10,394,986Model order reduction in transistor level timing201910,360,329Multi-cycle signal identification for static timing analysis201910,325,059Incremental common path pessimism analysis201910,031,988Model order reduction in transistor level timing20189,836,572Incremental common path pessimism analysis20179,785,737'Parallel multi-threaded common path pessimism removal in multiple paths'20179,760,665'Validating variation of timing constraint measurements'20179,760,664'Validating variation of timing constraint measurements'20179,690,899'Prioritized path tracing in statistical timing analysis of integrated circuits'20179,659,121'Deterministic and statistical timing modeling for differential circuits'20179,613,171'Multi-cycle signal identification for static timing analysis'20179,501,608'Timing analysis of circuits using sub-circuit timing models'20168,776,004'Method for improving static timing analysis and optimizing circuits using reverse merge'20148,655,634'Modeling loading effects of a transistor network'20148,201,120'Timing point selection for a static timing analysis in the presence of interconnect electrical elements'20128,112,735'Affinity-based clustering of vectors for partitioning the columns of a matrix'20127,958,484'Affinity-based clustering of vectors for partitioning the columns of a matrix'20117,870,515'System and method for improved hierarchical analysis of electronic circuits'20117,643,981'Pulse waveform timing in EinsTLT templates'20107,353,359'Affinity-based clustering of vectors for partitioning the columns of a matrix'20087,325,210'Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect'20086,763,504'Method for reducing RC parasitics in interconnect networks of an integrated circuit'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2019Patents assigned to IBM (22)· patent assignee history
2004–2019Based in Fishkill, NY, US· patent location history
2012–2014Patents assigned to RAO VASANT (4)· patent assignee history
2012–2014Patents assigned to KALAFALA KERIM (2)· patent assignee history
2012–2014Patents assigned to SOREFF JEFFREY P (2)· patent assignee history
2014Patents assigned to HATHAWAY DAVID J (2)· patent assignee history
2016Based in Hopewell Junction, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 2004–2019 |
| RAO VASANTself | 4 | 2012–2014 |
| HATHAWAY DAVID J | 2 | 2014 |
| KALAFALA KERIM | 2 | 2012–2014 |
| SOREFF JEFFREY P | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fishkill, New York, US | 21 | 2004–2019 |
| Hopewell Junction, New York, US | 1 | 2016 |