Inventor
Yuhao Luo
Inventor
San Jose, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution12%
H02JElectric power networks9%
Y10TTechnical subjects covered by former us classification9%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G01RMeasuring electric variables2%
PatentTitleYear
9,685,781'Solar photovoltaic system and a method for energy harvest optimization thereof and a method for fault detection thereof'20179,608,447'Solar photovoltaic three-phase micro-inverter and a solar photovoltaic generation system'20179,543,854'Solar photovoltaic three-phase micro-inverter system and a method for improving the conversion efficiency thereof'20179,520,721'Solar photovoltaic three-phase micro-inverter and solar photovoltaic power generation system'20168,343,795'Method to break and assemble solar cells'20138,120,075'Semiconductor device with improved trenches'20127,956,385'Circuit for protecting a transistor during the manufacture of an integrated circuit device'20117,936,006'Semiconductor device with backfilled isolation'20117,875,543'Strain-silicon CMOS using etch-stop layer and method of manufacture'20117,851,313'Semiconductor device and process for improved etch control of strained silicon alloy trenches'20107,772,093'Method of and circuit for protecting a transistor formed on a die'20107,670,923'Method of fabricating strain-silicon CMOS'20107,673,270'Method and apparatus for compensating an integrated circuit layout for mechanical stress effects'20107,655,991'CMOS device with stressed sidewall spacers'20107,635,843'In-line reliability test using E-beam scan'20097,429,526'Method of forming silicide gate with interlayer'20087,429,775'Method of fabricating strain-silicon CMOS'20087,423,283'Strain-silicon CMOS using etch-stop layer and method of manufacture'20087,214,629'Strain-silicon CMOS with dual-stressed film'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2012Patents assigned to XILINX INC (14)· patent assignee history
2007–2013Based in San Jose, CA, US· patent location history
2008Based in 5775 Morehouse Drive, CA, US· patent location history
2012–2016Patents assigned to LUO YUHAO (3)· patent assignee history
2012Patents assigned to NAYAK DEEPAK KUMAR (1)· patent assignee history
2013Patents assigned to LING ZHI-MIN (1)· patent assignee history
2016–2017Patents assigned to ALTENERGY POWER SYSTEM INC (4)· patent assignee history
2016Based in Jiaxing, CN· patent location history
2017Based in Zhejiang, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 14 | 2007–2012 |
| ALTENERGY POWER SYSTEM INC | 4 | 2016–2017 |
| LUO YUHAOself | 3 | 2012–2016 |
| LING ZHI-MIN | 1 | 2013 |
| NAYAK DEEPAK KUMAR | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 14 | 2007–2013 |
| Zhejiang, CN | 3 | 2017 |
| Jiaxing, CN | 1 | 2016 |
| 5775 Morehouse Drive, California, US | 1 | 2008 |