Inventor
Robert N. Hasbun
Inventor
Shingle Springs, CA, US
Overview
Patents· 81 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
G11CStatic stores22%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G06TImage data processing or generation, in general2%
G06VImage or video recognition or understanding2%
H04MTelephonic communication2%
G02BOptical elements, systems or apparatus1%
G07CTime or attendance registers1%
PatentTitleYear
11,119,561Non-volatile memory system or sub-system202111,055,000Apparatuses and methods for counter update operations202111,010,092Prefetch signaling in memory system or sub-system202111,003,388Prefetch signaling in memory system or sub system202110,978,116Multiple concurrent modulation schemes in a memory system202110,956,333Prefetching data based on data transfer within a memory system202110,942,854Prefetch management for memory202110,904,052Multiplexing distinct signals on a single pin of a memory device202110,877,622Detection of structured light for depth sensing202010,845,866Non-volatile memory system or sub-system202010,839,874Indicating latency associated with a memory request in a system202010,839,536Depth sensing using grid light patterns202010,832,748Memory system that supports dual-mode modulation202010,754,578Memory buffer management and bypass202010,725,913Variable modulation scheme for memory device access or operation202010,719,248Apparatuses and methods for counter update operations202010,714,159Indication in memory system or sub-system of latency associated with performing an access command202010,649,687Memory buffer management and bypass202010,490,245Memory system that supports dual-mode modulation201910,446,198Multiple concurrent modulation schemes in a memory system201910,355,893Multiplexing distinct signals on a single pin of a memory device201910,147,926Battery package including electrode having recessed region of electrode material layer exposing a portion of a conductive layer and method of making the same20189,857,864'Systems and methods for reducing power consumption in a memory architecture'20189,576,398'Pixelated light shutter mechanisms for improving contrast between computer-generated images and an ambient visible environment'20179,368,285'Power cell embedded in enclosure'20167,971,232'Setting group policy by device ownership'20117,818,559'Boot negotiation among multiple boot-capable devices'20107,698,739'Updating code with validation'20107,389,425'Biometric-based authentication in a nonvolatile memory device'20087,174,416'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'20077,062,623'Method and device for providing hidden storage in non-volatile memory'20066,839,823'Increased reliability of data stored on flash memory in applications sensitive to power-loss'20056,834,323'Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory'20046,775,776'Biometric-based authentication in a nonvolatile memory device'20046,732,306'Special programming mode with hashing'20046,681,304'Method and device for providing hidden storage in non-volatile memory'20046,622,200'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'20036,449,735'Method and apparatus for providing improved diagnostic functions in a computer system'20026,412,040'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'20026,401,160'Method and apparatus to permit adjustable code/data boundary in a nonvolatile memory'20026,311,290'Methods of reliably allocating, de-allocating, re-allocating, and reclaiming objects in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'20016,295,619'Method and apparatus for error management in a solid state disk drive'20016,243,789'Method and apparatus for executing a program stored in nonvolatile memory'20016,226,728'Dynamic allocation for efficient management of variable sized data within a nonvolatile memory'20016,223,290'Method and apparatus for preventing the fraudulent use of a cellular telephone'20016,205,548'Methods and apparatus for updating a nonvolatile memory'20016,189,070'Apparatus and method for suspending operation to read code in a nonvolatile writable semiconductor memory'20016,182,188'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'20016,154,819'Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks'20006,088,759'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'20006,014,755'Method of managing defects in flash disk memories'20005,936,884'Multiple writes per a single erase for a nonvolatile memory'19995,937,434'Method of managing a symmetrically blocked nonvolatile memory having a bifurcated storage architecture'19995,893,135'Flash memory array with two interfaces for responding to RAS and CAS signals'19995,875,477'Method and apparatus for error management in a solid state disk drive using primary and secondary logical sector numbers'19995,867,721'Selecting an integrated circuit from different integrated circuit array configurations'19995,829,013'Memory manager to allow non-volatile memory to be used to supplement main memory'19985,822,781'Sector-based storage device emulator having variable-sized sector'19985,822,256'Method and circuitry for usage of partially functional nonvolatile memory'19985,815,434'Multiple writes per a single erase for a nonvolatile memory'19985,765,002'Method and apparatus for minimizing power consumption in a microprocessor controlled storage device'19985,740,349'Method and apparatus for reliably storing defect information in flash disk memories'19985,740,395'Method and apparatus for cleaning up a solid state memory disk storing floating sector data'19985,696,929'Flash EEPROM main memory in a computer system'19975,671,388'Method and apparatus for performing write operations in multi-level cell storage device'19975,640,529'Method and system for performing clean-up of a solid state disk during host command execution'19975,586,285'Method and circuitry for increasing reserve memory in a solid state memory disk'19965,581,723'Method and apparatus for retaining flash block structure data during erase operations in a flash EEPROM memory array'19965,577,194'Method of managing defects in flash disk memories'19965,563,828'Method and apparatus for searching for data in multi-bit flash EEPROM memory arrays'19965,553,261'Method of performing clean-up of a solid state disk while executing a read command'19965,544,312'Method of detecting loss of power during block erasure and while writing sector data to a solid state disk'19965,541,886'Method and apparatus for storing control information in multi-bit non-volatile memory arrays'19965,535,369'Method for allocating memory in a solid state memory disk'19965,479,633'Method of controlling clean-up of a solid state memory disk storing floating sector data'19955,475,693'Error management processes for flash EEPROM memory arrays'19955,473,753'Method of managing defects in flash disk memories'19955,471,604'Method for locating sector data in a memory disk by examining a plurality of headers near an initial pointer'19955,448,577'Method for reliably storing non-data fields in a flash EEPROM memory array'19955,437,020'Method and circuitry for detecting lost sectors of data in a solid state memory disk'19955,357,475'Method for detaching sectors in a flash EEPROM memory array'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2008Patents assigned to INTEL CORP (53)· patent assignee history
1994–2007Based in Shingle Springs, CA, US· patent location history
2000–2010Based in Placerville, CA, US· patent location history
2010–2011Patents assigned to MICROSOFT CORP (2)· patent assignee history
2010–2018Based in Fall City, WA, US· patent location history
2016–2018Patents assigned to AMAZON TECH INC (4)· patent assignee history
2019–2021Patents assigned to MICRON TECHNOLOGY INC (19)· patent assignee history
2019–2021Based in San Jose, CA, US· patent location history
2020Patents assigned to FACEBOOK TECH LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 53 | 1994–2008 |
| MICRON TECHNOLOGY INC | 19 | 2019–2021 |
| AMAZON TECH INC | 4 | 2016–2018 |
| FACEBOOK TECH LLC | 2 | 2020 |
| MICROSOFT CORP | 2 | 2010–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Shingle Springs, California, US | 41 | 1994–2007 |
| San Jose, California, US | 21 | 2019–2021 |
| Placerville, California, US | 13 | 2000–2010 |
| Fall City, Washington, US | 6 | 2010–2018 |